Infineon CYUSB3084FCAXIXQMA1

EZ-USB FX5 is a family of 5 Gbps USB peripheral controllers targeting next-generation USB applications in the camera, video, imaging, and data acquisition markets. The FX5 comprises dual Arm Cortex-M4 and M0+ core CPUs, 512 KB flash, 128 KB SRAM, 128 KB ROM, seven serial communication blocks (SCBs), a cryptographic accelerator, and a high-bandwidth data subsystem capable of DMA data transfers at up to 5 Gbps between LVDS/LVCMOS and USB ports. The high-bandwidth data subsystem also includes an additional 1 MB SRAM for USB data buffering. The FX5 further supports USB Type-C plug orientation detection and flip mux functionality without external logic.

• USB 3.2 Gen 1 (5 Gbps) device port
  • Integrated 5 Gbps and 480 Mbps PHY
  • USB Type-C plug orientation detection and correction
  • Up to 30 USB endpoints, 15 IN and 15 OUT; each endpoint configurable as Bulk, Isochronous, or Interrupt
• Dual-core CPU subsystem
  • 150 MHz Arm Cortex-M4F (CM4) CPU with single-cycle multiply, floating point (FP), and MPU
  • 100 MHz Arm Cortex-M0+ (CM0+) CPU with single-cycle multiply and MPU
• Memory subsystem
  • 512 KB on-chip application flash with read-while-write (RWW) support
  • 128 KB SRAM with power and data retention control
  • 128 KB ROM for device initialization, flash write, security, and OTP fuse programming
  • 1 MB SRAM for LVDS/LVCMOS-to-USB data buffering
  • 1024-bit OTP fuse array
• Dual-port General Programmable Interface (GPIF III)
  • LVDS/subLVDS multi-channel serial data bus receive mode
    • Each port consists of eight data lanes, one control lane, one clock lane, and seven LVCMOS control signals
    • Two ports combinable into a single 16-lane data link
    • Maximum data rate: 1.25 Gbps per lane in DDR-only receive mode; 625 Mbps per lane in SDR-only receive mode
  • LVCMOS parallel data bus transceiver mode
    • Each port consists of 16 data signals, one clock signal, and 10 control signals
    • Two ports combinable into a 32-bit wide data bus
    • RX up to 160 MHz DDR or SDR mode; TX 100 MHz SDR mode, 80 MHz DDR TX
• Peripheral IO subsystem — 48 shared IOs total
  • QSPI configurable as single, dual, quad, dual-quad, and octal interface
  • Seven SCBs configurable as I²C, UART, or SPI
  • Two-channel configurable audio interface
    • I²S master or slave mode, receive or transmit
    • PDM-to-PCM converter for microphones
  • One USB Full-Speed (FS) device for virtual COM port function
  • Seven TCPWM (Timer/Counter/PWM)
  • One CAN FD
  • GPIO: each peripheral IO configurable as GPIO
• Ultra-low power (ULP) and fine-grained power management
  • 1.7 V to 3.6 V operating voltage
  • Deep Sleep mode with SRAM retention
• Flexible clock options
  • 8 MHz IMO with ±2% accuracy
  • Low-power 32 kHz ILO
  • 24 MHz external crystal oscillator
  • PLL for frequency multiplication
  • FLL for IMO frequency multiplication
  • Integer and fractional peripheral clock dividers
• Security
  • ROM-based root of trust via uninterrupted secure boot
  • Staged authentication of executing images
  • Secure code execution of protected programs in execute-only mode
  • All debug and test access paths disableable
  • Eight protection contexts
  • Cryptographic accelerator
  • Hardware acceleration for symmetric and asymmetric encryption and hash functions
  • True Random Number Generation (TRNG)
• Package information
  • 169-ball, 10 × 10 × 1.2 mm, 13 × 13 ball array, 0.75 mm pitch FBGA
• Development tools
  • ModusToolbox software for cross-platform code development with a comprehensive suite of tools and software libraries
  • Firmware examples including USB3 Vision (U3V), UVC, UAC, HID, CDC, and vendor-specific classes
  • Infineon Developer Community connecting EZ-USB developers worldwide 24/7

• Machine vision / industrial cameras
• HDMI/SDI high-bandwidth frame grabbers
• 3D scanners
• Video conferencing cameras
• Document scanners
• Streaming spectrum analyzers
• Medical imaging cameras
• High-bandwidth instruments