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TI CD4027BF3ARoHS

Manufacturer
MPN
CD4027BF3A
LCSC Part #
C3827160
Packaging
CDIP-16
Customer #
Key Attributes
3V~18V 1 2 45ns@15V,50pF CDIP-16 Flip Flops RoHS
Datasheetpdf iconTI CD4027BF3A
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QtyUnit PriceTotal Amount
1+$ 28.3625$ 28.36
25+$ 26.8442$ 671.11
Standard Packaging25/Full Tube
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Flip Flops
ManufacturerTI
PackagingCDIP-16
Voltage - Supply3V~18V
Number of Bits per Element1
Output TypeComplementary type
Operating Temperature-55℃~+125℃
SeriesCD40
Synchronous/AsynchronousAsynchronous
Current - Output High(IOH)3.4mA
Number of Elements2
Current - Output Low(IOL)3.4mA
Setup Time50ns
Quiescent Current4uA
Hold Time-
Propagation Delay45ns@15V,50pF
Trigger TypeRising Edge

Introduction

AI Translation

The CD4027B is a monolithic integrated circuit chip that contains two identical complementary-symmetry J-K flip-flops. Each flip-flop provides separate J, K, set, reset, and clock input signals, as well as buffered Q and Q (with an overbar) output signals. With these inputs/outputs, compatible operation with the RCA - CD4013B dual D-type flip-flop can be achieved. The CD4027B is suitable for performing control, register, and switching functions. The logic levels at the J and K inputs and internal self-manipulation control the state of each flip-flop; changes in the flip-flop state are synchronized with the positive transition of the clock pulse. The set and reset functions are independent of the clock and are activated when a high-level signal appears at the set or reset input. The CD4027B is available in a 16-pin hermetic dual in-line ceramic package (suffix F3A), a 16-pin dual in-line plastic package (suffix E), a 16-pin small outline package (suffixes M, M96, MT, and NSR), and a 16-pin thin shrink small outline package (suffixes PW and PWR).

Features

AI Translation
  • Set/reset latch operation — holds state indefinitely at high or low clock level
  • Medium-speed operation — clock switching speed of 16MHz (typical) at 10V
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current at 20V
  • Maximum input current of 1μA at 18V over full package temperature range; 100nA at 18V and 25℃
  • Noise margin (over full package temperature range):
    • 1V at VDD = 5V
    • 2V at VDD = 10V
    • 2.5V at VDD = 15V
  • 5V, 10V, and 15V parametric ratings comply with JEDEC Tentative Standard No. 138, the standard specification for describing CMOS device families

Applications

AI Translation
  • Registers
  • Counters
  • Control circuits