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RENESAS HSP48908JC-32

Manufacturer
MPN
HSP48908JC-32
LCSC Part #
C3587934
Packaging
-
Customer #
Key Attributes
Specialized ICs
Datasheetpdf iconRENESAS HSP48908JC-32
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1+$ 39.433$ 39.43
200+$ 15.2602$ 3052.04
500+$ 14.7249$ 7362.45
1,000+$ 14.4596$ 14459.60
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Specialized ICs
ManufacturerRENESAS
Packaging-
FunctionHardware MAC acceleration;Circular buffer support

Introduction

AI Translation

A high speed Two Dimensional Convolver which provides a single chip implementation of a videodatarate 3x3 kernel convolution on two dimensional data. It eliminates the need for external data storage through the use of the on-chip row buffers which are programmable for row lengths up to 1024 pixels.

There are internal register banks for storing two independent 3x3 filter kernels, thus facilitating the implementation of adaptive filters and multiple filter operations on the same data. The pixel data path also includes an on-chip ALU for performing real-time arithmetic and logical pixel point operations.

Data is provided to the device in a raster scan noninterlaced fashion, and is internally buffered on images up to 1024 pixels wide for the 3x3 convolution operation. Images with larger rows and convolution with larger kernel sizes can be accommodated by using external row buffers and/or multiple devices. Coefficient and pixel input data are 8-bit signed or unsigned integers, and the 20-bit convolver output guarantees no overflow for kernel sizes up to 4x4. Larger kernel sizes can be implemented however, since the filter coefficients will normally be less than their maximum 8-bit values.

The device is manufactured using an advanced CMOS process, and is a low power fully static design. The configuration of the device is controlled through a standard microprocessor interface and all inputs/outputs are TTL compatible.

Features

AI Translation
  • Single Chip 3 x 3 Kernel Convolutlon
  • Programmable On-Chip Row Buffers
  • DC to 32MHz Ciock Rate
  • Cascadable for Larger Kernels and Images
  • On-Chip 8-Bit ALU
  • Dual Coefficlent Mask Registers, Switchable in a Single Clock Cycle
  • 8-Bit Signed or Unsigned input and Coefficlent Data
  • 20-Blt Extended Precision Output
  • Standard μP Interface
  • Low Power CMOS

Applications

AI Translation
  • Image Filtering
  • Edge Detection
  • Adaptive Filtering
  • Real Tlme Video Fllters