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TI CD40109BE product image
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TI CD40109BERoHS

Manufacturer
TI
MPN
CD40109BE
LCSC Part #
C353967
Packaging
PDIP-16
Customer #
Key Attributes
4 1 PDIP-16 Translators, Level Shifters RoHS
Datasheetpdf iconTI CD40109BE
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QtyUnit Price(Reference Only)Total Amount
1+$ 0.6092$ 0.61
10+$ 0.4895$ 4.90
25+$ 0.4281$ 10.70
100+$ 0.3698$ 36.98
500+$ 0.3345$ 167.25
1,000+$ 0.3161$ 316.10
Standard Packaging25/Full Tube
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Translators, Level Shifters
ManufacturerTI
PackagingPDIP-16
output typeTri-State
Interface-
Operating Temperature-55℃~+125℃
Number of Elements4
Channel TypeUnidirectional
FeaturesOutput enable high-impedance
Voltage - Supply3V~18V;3V~18V
Number of Circuits1
Current - Output High(IOH)-
Current - Output Low(IOL)-
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Features

AI Translation
  • High-Voltage Types (20-Volt Rating)
  • Does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. No restrictions on the sequence of application of VDD, VCC, or the input signals.
  • With one exception, no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSS and at least 0.7VCC; VCC may exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC > VDD, it will operate as a high-to-low level-shifter.
  • Features individual three state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output.
  • The CD40109B-Series types are supplied in 16-lead ceramic dual-in-line packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

Applications

AI Translation
  • High-or-low fevel-shifting with thrse-state outputs for unidirectional or bidirectional bussing
  • Isolation of logic subsystems using separ ate power supplies from supply soquenc. ing. supply loss and supply regulation considerations
  • Independence of power supply sequence considerations-- Vcc can oxceed VpD. input signals can exceed both Vcc and VDD
  • Up and down level-shifting capability
  • Three-state outputs with seperate enable controls
  • Standardized, sy mmetrical output characteristics
  • 100% testad for quiescent current at 20 V
  • Maximum input current of μA at 18 V over full package-temperature range; 100 nA at 18 V and
  • Noise margin (fufl package-temperature range) = 1 V at Vcc = 5 v, Vdd = 10 v = 2 V at Vcc = 10 v, Vdd = 15 v
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Speclflcations for Description of 'B' Serles CMOs Devices"