AMD/XILINX XA7A50T-1CSG325Q

Xilinx XA Artix-7 (Automotive) FPGAs are optimized for the lowest cost and power with small form-factor packaging for high-volume automotive applications. Designers can leverage more logic per watt compared to the Spartan-6 family. Built on a state-of-the-art high-performance/low-power (HPL) 28 nm high-k metal gate (HKMG) process technology, XA Artix-7 FPGAs redefine low-cost alternatives with more logic per watt. Unparalleled increase in system performance with 52 Gb/s I/O bandwidth, 100,000 logic cell capacity, 264 GMAC/s DSP, and flexible built-in DDR3 memory interfaces enable a new class of high-throughput, low-cost automotive applications. XA Artix-7 FPGAs also offer many high-end features, such as integrated advanced Analog Mixed Signal (AMS) technology. Analog becomes the next level of integration through the seamless implementation of independent dual 12-bit, 1 MSPS, 17-channel analog-to-digital converters. Most importantly, XA Artix-7 FPGAs proudly meet the high standards of the automotive grade with a maximum temperature of 125℃.

• Automotive Temperatures: I-Grade: Tj = -40℃ to +100℃; Q-Grade: Tj = -40℃ to +125℃
• ISO-TS16949 compliant
• AEC-Q100 qualification
• Production Part Approval Process (PPAP) documentation Beyond AEC-Q100 qualification is available upon request
• Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory
• 36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering
• Sub-watt performance in 100,000 logic cells
• High-performance SelectIO™ technology with support for DDR3 interfaces up to 800 Mb/s
• High-speed serial connectivity with built-in serial transceivers from 500 Mb/s to maximum rates of 6.25 Gb/s, enabling 50 Gb/s peak bandwidth (full duplex)
• A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors
• Single-ended and differential 1/o standards with speeds of up to 1.25 Gb/s
• 240 DSP48E1 slices with up to 264 GMACs of signal processing
• Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter
• Integrated block for PCI Express (PCIe), for up to x4 Gen2 Endpoint
• Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction
• Low-cost wire-bond packaging, offering easy migration between family members in the same package, all packages available Pb-free
• Designed for high performance and lowest power with 28 nm, HKMG, HPL process, 1.0V core voltage process technology
• Strong automotive-specific third-party ecosystem with IP, development boards, and design services