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RENESAS R5F10WLEAFA#10RoHS

Manufacturer
MPN
R5F10WLEAFA#10
LCSC Part #
C3231129
Packaging
LQFP-64(12x12)
Customer #
Key Attributes
RL78 16 Bit 24MHz 42 LQFP-64(12x12) Microcontrollers RoHS
Datasheetpdf iconRENESAS R5F10WLEAFA#10
In-Stock: 10
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QtyUnit PriceTotal Amount
1+$ 3.3766$ 3.38
10+$ 3.297$ 32.97
30+$ 3.245$ 97.35
100+$ 3.1914$ 319.14
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/Microcontrollers
ManufacturerRENESAS
PackagingLQFP-64(12x12)
ADC (Bit)10bit
Operating Temperature-40℃~+85℃
Program Memory TypeFLASH
Voltage - Supply1.6V~5.5V
EEPROM4KB
Program Storage Size64KB
CPU CoreRL78
Core Size16 Bit
CPU Maximum Speed24MHz
Oscillator TypeBuilt-in
Number of I/O42

Introduction

AI Translation

Integrated LCD controller/driver, True Low Power Platform (as low as 71 μA A Hz, and 0.61 μA for RTC + LVD), 1.6 V to 5.5 V operation, 16 to 128 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Applications

Features

AI Translation
  • Ultra-low power consumption technology
    • VDD = single power supply voltage of 1.6 to 5.5 V which can operate a 1.8 V device at a low voltage
    • HALT mode
    • STOP mode
    • SNOOZE mode
  • RL78 CPU core
    • CISC architecture with 3-stage pipeline
    • Minimum instruction execution time: Can be changed from high speed (0.04167 μs : @ 24 MHz operation with highspeed on-chip oscillator) to ultra-low speed 30.5 μs : @ 32.768 kHz operation with subsystem clock
    • Address space: 1 MB
    • General-purpose registers: (8-bit register × 4 banks
    • On-chip RAM: 1 to 8 KB
  • Code flash memory
    • Code flash memory: 16 to 128 KB
    • Block size: 1 KB
    • Prohibition of block erase and rewriting (security function)
    • On-chip debug function
    • Self-programming (with boot swap function/flash shield window function)
  • Data flash memory
    • Data flash memory: 4 KB
    • Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory.
    • Number of rewrites: 1,000,000 times (TYP.)
    • Voltage of rewrites: VDD = 1.8 to 5.5 V
  • High-speed on-chip oscillator
    • Select from 48 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz
    • High accuracy: ±1.0 % (VDD = 1.8 to 5.5 V, TA = -20 to +85℃)
  • Operating ambient temperature
    • TA = -40 to +85℃ (A: Consumer applications)
    • TA = -40 to +105℃ (G: Industrial applications)
  • Power management and reset function
    • On-chip power-on-reset (POR) circuit
    • On-chip voltage detector (LVD) (Select interrupt and reset from 14 levels)
  • DMA (Direct Memory Access) controller
    • 4 channels
    • Number of clocks during transfer between 8/16-bit SFR and internal RAM: 2 clocks
  • Multiplier and divider/multiply-accumulator
    • 16 bits × 16 bits = 32 bits (Unsigned or signed)
    • 32 bits ÷ 32 bits = 32 bits (Unsigned)
    • 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
  • Communication interfaces
    • Simplified SPI (CSI): 2 channels
    • UART/UART (LIN-bus supported): 3, 4 channels/1 channel
    • I²C/Simplified I²C communication: 1 channel/2 channels
  • Timer
    • 16-bit timer: 8 channels (with remote control output function)
    • 16-bit timer KB20 (IH): 1 channel (IH-only PWM output function)
    • 12-bit interval timer: 1 channel
    • Real-time clock 2: 1 channel (calendar for 99 years, alarm function, and clock correction function)
    • Watchdog timer: 1 channel (operable with the dedicated lowspeed on-chip oscillator)
  • A/D converter
    • 8/10-bit resolution A/D converter (VDD = 1.6 to 5.5 V)
    • Analog input: 9 to 12 channels
    • Internal reference voltage (1.45 V) and temperature sensor
  • Comparator
    • 2 channels
    • Operation mode: Comparator high-speed mode, comparator low-speed mode, or window mode
    • External reference voltage and internal reference voltage are selectable
  • LCD controller/driver
    • Segment signal output: 36 (32) to 51 (47)
    • Common signal output: 4 (8)
    • Internal voltage boosting method, capacitor split method, and external resistance division method are switchable
  • I/O port
    • I/O port: 49 to 65 (N-ch open drain I/O [withstand voltage of 6 V]: 2, N-ch open drain I/O [VDD withstand voltage]: 12 to 18)
    • Can be set to N-ch open drain, TTL input buffer, and on-chip pull-up resistor
    • Different potential interface: Can connect to a 1.8/2.5/3 V device
    • On-chip key interrupt function
    • On-chip clock output/buzzer output controller
  • Others
    • On-chip BCD (binary-coded decimal) correction circuit