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XTX XT61M2G8C2TM-B8BEA product image
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XTX XT61M2G8C2TM-B8BEARoHS

Manufacturer
XTXAsian Brands
MPN
XT61M2G8C2TM-B8BEA
LCSC Part #
C29781627
Packaging
BGA-162(10.5x8)
Customer #
Key Attributes
NAND Flash + Low Power DDR2 SDRAM
Datasheetpdf iconXTX XT61M2G8C2TM-B8BEA
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QtyUnit Price(Reference Only)Total Amount
1+$ 8.1702$ 8.17
10+$ 7.0191$ 70.19
30+$ 6.3195$ 189.59
100+$ 5.7324$ 573.24
Standard Packaging242/Full Tray
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Products Specifications

All
TypeDescription
CategoryOffice Supplies/Storage Products/Specialized Memory Products
ManufacturerXTX
PackagingBGA-162(10.5x8)
RAM architectureDDR SDRAM
Flash architectureNAND FLASH
Type of memory1 FLASH +1 RAM
Memory Size of Flash2Gbit
Memory Size of RAM1Gbit
Clock Frequency(fc)533MHz
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Introduction

AI Translation

XTX nMCP is a Multi-Chip Packaged memory which combines NAND flash memory and LPDDR2 (Low Power Double Data Rate) SDRAM. The NAND flash memory provides the most cost-effective solution for the non-volatile solid state mass storage market, while the LPDDR2 is an excellent solution for large volatile but fast storage applications such as random/temporary data access. XTX nMCP is suitable for use in data memory of portable electronic devices to reduce its square size and power consumption at the same time. The NAND flash memory and LPDDR2 SDRAM in it could be operated individually.

Features

AI Translation
  • <NAND flash>
    • Single Level per Cell (SLC) Technology
    • ECC requirement: 8bit/512Bytes
    • Power Supply Voltage Voltage range: 1.7V - 1.95V
    • Organization Page size: x8 (2048 + 128) bytes; 128 - bytes spare area Block size: x8 (128k + 8k) bytes 2008 block (min) ~ 2048 block (max)
    • Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy
    • Access time Cell array to register: 25µs (max) Serial Read Cycle: 25 ns (min) (CL = 50pF)
    • Program/Erase time Auto Page Program: 300 µs /page (typ.) Auto Block Erase: 3.5 ms/block( typ.)
    • Reliability 10 Year Data Retention (typ.)
  • <LPDDR2>
    • Ultra low - voltage core and I/O power supplies – VDD2 = 1.14 - 1.30V – VDDCA/VDDO = 1.14 - 1.30V – VDD1 = 1.70 - 1.95V
    • Clock frequency range 533 – 10 MHz (data rate range: 1066 – 20 Mb/s/pin)
    • Four - bit prefetch DDR architecture
    • Eight internal banks for concurrent operation
    • Multiplexed, double data rate, command/address inputs; commands entered on every CK edge
    • Bidirectional/differential data strobe per byte of data (DQS/DQS#)
    • Programmable READ and WRITE latencies (RL/WL)
    • Programmable burst lengths: 4, 8, or 16
    • Per - bank refresh for concurrent operation
    • On - chip temperature sensor to control self - refresh rate (SR not supported > 105℃)
    • Partial - array self - refresh (PASR)
    • Deep power - down mode (DPD)
    • Selectable output drive strength (DS)
    • Clock stop capability
    • RoHS - compliant, “green” packaging