Infineon/CYPRESS CY7C2665KV18-450BZI

The CY7C2663KV18, and CY7C2665KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR ||+ architecture. Similar to QDR II architecture, QDR ||+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR ||+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR ||+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 18-bit words (CY7C2663KV18), or 36-bit words (CY7C2665KV18) that burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input clocks (K and K), memory bandwidth is maximized while simplifying system design by eliminating bus “turn arounds”. These devices have an ODT feature supported for D[x:0], BWS[x:0], and K/K inputs, which helps eliminate external termination resistors, reduce cost, reduce board area, and simplify board routing. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

• Separate independent read and write data ports
• Supports concurrent transactions
• 550-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz at 550 MHz)
• Available in 2.5-clock cycle latency
• Two input clocks (K and K) for precise DDR timing
• Static random access memory (SRAM) uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• On-die termination (ODT) feature
• Supported for D[x:0], BWS[x:0], and K/K inputs
• Single multiplexed address input bus latches address inputs for read and write ports
• Separate port selects for depth expansion
• Synchronous internally self-timed writes
• Quad data rate (QDR ||+) operates with 2.5-cycle read latency when DOFF is asserted high
• Operates similar to QDR I device with 1 cycle read latency when DOFF is asserted low
• Available in x18, and x36 configurations
• Full data coherency, providing most current data
• Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD
• Supports both 1.5 V and 1.8 V I/O supply
• High-speed transceiver logic (HSTL) inputs and variable drive HSTL output buffers
• Available in 165-ball fine-pitch ball grid array (FBGA) package (15x17x1.4 mm)
• Offered in both Pb-free and non Pb-free packages
• JTAG 1149.1 compatible test access port
• Phase locked loop (PLL) for accurate data placement