Infineon/CYPRESS CY7C65642-48AXC

HX2VL is next generation family of high-performance, very low-power USB 2.0 hub controllers. HX2VL has integrated upstream and downstream transceivers; a USB serial interface engine (SIE); USB hub control and repeater logic; and transaction translator (TT) logic. External components such as voltage regulator and pull-up/pull-down resistors are also integrated, reducing the overall BOM required to implement a USB hub system. The CY7C65642 is a part of the HX2VL portfolio with four downstream ports and an independent TT dedicated for each downstream port. This device option is for low-power but high-performance applications that require up to four downstream ports. The CY7C65642 is available in 48-pin TQFP and 28-pin QFN package options.

• High-performance, low-power USB 2.0 hub, optimized for low-cost designs with minimum bill-of-material (BOM).
• USB 2.0 hub controller - Compliant with USB2.0 specification, TID# 30000059 - Up to four downstream ports support - Downstream ports are backward compatible with FS, LS - Multiple translator (TT), one per downstream port for maximum performance.
• Very low-power consumption
  • Supports bus-powered and self-powered modes
  • Auto switching between bus-powered and self-powered
  • Single MCU with 2 K ROM and 64 byte RAM
  • Lowest power consumption. Highly integrated solution for reduced BOM cost
  • Internal regulator – single power supply 5 V required.
  • Provision of connecting 3.3 V with external regulator.
  • Integrated upstream pull-up resistor
  • Integrated pull-down resistors for all downstream ports
  • Integrated upstream/downstream termination resistors
  • Integrated port status indicator control
  • 12-MHz ± 500 ppm external crystal with drive level 600 μW (integrated PLL) clock input with optional 27/48-MHz oscillator clock input.
  • Internal power failure detection for ESD recovery
• Downstream port management
  • Support individual and ganged mode power management
  • Overcurrent detection
  • Two status indicators per downstream port
• Maximum configurability
  • VID and PID are configurable through external EEPROM
  • Number of ports, removable/non-removable ports are configurable through EEPROM and I/O pin configuration
  • I/O pins can configure gang/individual mode power switching, reference clock source and polarity of power switch enable pin
  • Configuration options also available through mask ROM
• Available in space saving 48-pin TQFP (7×7 mm) and 28-pin QFN (5×5 mm) packages
• Supports 0°C to +70°C temperature range