Infineon/CYPRESS CY62128DV30LL-70ZRI

The CY62128DV30 is a high-performance CMOS static RAM organized as 128K words × 8 bits. This device employs advanced circuit design to deliver ultra-low operating current, making it ideal for extending battery life in portable applications such as mobile phones. The device also features automatic power-down, which reduces power consumption by up to 90% when the address is not switching. When Chip Enable 1 (CE1 bar) is high or Chip Enable 2 (CE2) is low, the device enters standby mode, reducing power consumption by more than 99%. The I/O pins (I/O0 through I/O7) are placed in a high-impedance state when Chip Enable 1 (CE1 bar) is high or Chip Enable 2 (CE2) is low, when Output Disable (OE is high), or during a write operation (Chip Enable 1 (CE1 bar) is low, Chip Enable 2 (CE2) is high, and Write Enable (WE) is low). To write data to the device, Chip Enable 1 (CE1 bar) must be driven low, Chip Enable 2 (CE2) high, and Write Enable (WE) low; data present on the 8 I/O pins is then written to the location specified by address pins A0 through A16. To read data from the device, Chip Enable 1 (CE1 bar) must be driven low, Chip Enable 2 (CE2) high, Output Enable (OE) low, and Write Enable (WE) high; under these conditions, the contents of the memory cell specified by the address pins appear on the I/O pins.

• Ultra-high speed: 55 and 70 ns
• Wide voltage range: 2.2V to 3.6V
• Pin-compatible with CY62128V
• Ultra-low active power consumption Active current: 0.85 mA typical at f = 1 MHz Active current: 5 mA typical at f = fMAX
• Ultra-low standby power consumption
• Easy memory expansion via CE1, CE2, and OE functions Automatic power-down when deselected
• Available in lead-free and leaded 32-pin SOIC, 32-pin TSOP, and 32-pin small TSOP packages, and leaded 32-pin reverse TSOP package

• Portable applications
• Mobile phones