Infineon/CYPRESS CY7C1041BN-15VIT

The CY7C1041BN is a high-performance CMOS static random access memory organized as 262,144 words × 16 bits. To write data to the device, the Chip Enable (CE) and Write Enable (WE) inputs must be driven low. When Byte Low Enable (BLE) is low, data from the I/O pins (I/O₀ through I/O₇) is written to the location specified by the address pins (A₀ through A₁₇); when Byte High Enable (BHE) is low, data from the I/O pins (I/O₈ through I/O₁₅) is written to the location specified by the address pins (A₀ through A₁₇). To read data from the device, CE and Output Enable (OE) must be driven low while Write Enable (WE) is held high. When BLE is low, data from the memory location specified by the address pins appears on I/O₀ through I/O₇; when BHE is low, data from the memory location appears on I/O₈ through I/O₁₅. The input/output pins (I/O₀ through I/O₁₅) are placed in a high-impedance state when the device is deselected (CE high), the output is disabled (OE high), both BHE and BLE are disabled (BHE and BLE high), or during a write operation (CE low and WE low). The CY7C1041BN is available in standard 44-pin 400-mil wide-body SOJ and 44-pin TSOP II packages, featuring a center power and ground (innovative) pin configuration.

• Temperature Range
• Commercial: 0°C to 70°C
• Industrial: -40°C to 85°C
• Automotive Grade A: -40°C to 85°C
• High Speed
• t_AA = 15 ns
• Low Active Power Consumption
• 1540 mW (max)
• Low CMOS Standby Power (L Version)
• 2.75 mW (max)
• 2.0V Data Retention (400 μW at 2.0V retention)
• Automatic Power-Down When Deselected
• TTL-Compatible Inputs and Outputs
• CE and OE for Easy Memory Expansion
• Available in Lead-Free and Leaded 44-Pin TSOP II and Molded 44-Pin (400-mil) SOJ Packages