Infineon/CYPRESS CY7C1463AV33-133CKJ

CY7C1461AV33/CY7C1463AV33 are 3.3V, 1M×36 / 2M×18 synchronous flow-through burst SRAMs specifically designed to support unlimited consecutive read and write operations without wait states. These devices feature advanced No Bus Latency (NoBL) logic that transfers data every clock cycle, enabling continuous read/write operations. This characteristic significantly improves data throughput through the SRAM, making it particularly suitable for systems requiring frequent write-to-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by a Clock Enable (CEN) signal; when CEN is deasserted, operation is suspended and the previous clock cycle is extended. The maximum access latency from the rising clock edge is 6.5 ns (133 MHz device). Write operations are controlled by two or four Byte Write Select (B̄W̄X̄) signals and a Write Enable (W̄Ē) input. All write operations are performed through an on-chip synchronous self-timed write circuit. Three synchronous Chip Enables (C̄Ē1, CE2, C̄Ē3) and one asynchronous Output Enable (ŌĒ) facilitate memory bank selection and output tri-state control. To prevent bus contention, the output drivers synchronously enter tri-state during the data portion of a write sequence.

• No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles, supporting zero wait-state bus operation up to 133 MHz with data transfer every clock cycle
• Pin-compatible with ZBT devices, functionally equivalent
• Internal self-timed output buffer control, no OE required
• Registered inputs for flow-through operation
• Byte write capability
• 3.3 V and 2.5 V I/O supply voltages
• Fast clock-to-output time of 6.5 ns (for 133 MHz devices)
• Clock Enable (CEN) pin for enabling clock and pausing operation
• Synchronous self-timed write operation
• Asynchronous output enable
• CY7C1461AV33 and CY7C1463AV33 available in JEDEC standard lead-free 100-pin TQFP package
• Three chip enables for easy depth expansion
• Automatic power-down via ZZ mode or CE deselection
• Burst capability — linear or interleaved burst order
• Low standby power consumption