Infineon/CYPRESS CY7C330-33JC

This device is a high-performance, programmable logic device with an architecture optimized to enable users to build high-performance synchronous state machines conveniently and efficiently. Its unique architecture — featuring configurable input/output macrocells, bidirectional I/O capability, input registers, and three independent clocks — allows users to design high-performance machines that can communicate with each other or with microprocessors via a user-defined-width bidirectional parallel bus.

• Twelve I/O macrocells, each featuring: tri-state I/O pin with register, input register clock selection multiplexer, feedback multiplexer, output enable multiplexer.
• All twelve macrocell state registers are hideable.
• User-configurable state register type: JK, RS, T, or D.
• One input multiplexer per I/O macrocell pair, allowing I/O pins associated with hidden macrocell state registers to be retained as inputs.
• Four dedicated hidden registers.
• Eleven dedicated, registered inputs.
• Three independent clocks: two input clocks and one output clock.
• Per I/O pin common (pin 14 controlled) or product term controlled output enable.
• 256 product terms, 32 per macrocell pair, with flexible allocation.
• Global, synchronous, product term controlled state register set and reset, with product term inputs synchronized by input clock.
• 66 MHz operating frequency, 3 ns input setup time, 12 ns clock-to-output time, 15 ns input register clock-to-state register clock time.
• Low power consumption, typical operating current 130 mA.
• 28-pin, 300-mil pitch DIP and leaded chip carrier packages.
• Erasable and reprogrammable.