Infineon/CYPRESS S27KL0641DABHI033

The Cypress 64-Mb HyperRAM device is a high-speed CMOS, self-refresh Dynamic RAM (DRAM), with a HyperBus interface. The Cypress 128-Mb HyperRAM is a dual-die stack of 64-Mb HyperRAM devices in a single package. The Random Access Memory (RAM) array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the RAM array when the memory is not being actively read or written by the HyperBus interface master (host). Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. Hence, the memory can also be described as Pseudo Static RAM (PSRAM). Because the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host not perform read or write burst transfers that are long enough to block the necessary internal logic refresh operations when they are needed. The host is required to limit the duration of transactions and allow additional initial access latency, at the beginning of a new transaction, if the memory indicates a refresh operation is needed. HyperBus is a low-signal-count, Double Data Rate (DDR) interface that achieves high-speed read and write throughput. The DDR protocol transfers two data bytes per clock cycle on the DQ input/output signals. A read or write transaction on HyperBus consists of a series of 16-bit wide, one clock cycle data transfers at the internal HyperRAM core with two corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ signals. All inputs and outputs are LV-CMOS compatible. Ordering Part Number (OPN) device versions are available for core (VCC) and IO buffer (VCCQ) supplies of either 1.8 V or 3.0 V (nominal). Command, address, and data information is transferred over the eight HyperBus DQ[7:0] signals. The clock is used for information capture by a HyperBus slave device when receiving command, address, or data on the DQ signals. Command or Address values are center aligned.

• HyperRAM Low Signal Count Interface
  • 3.0 V I/O, 11 bus signals
  • Single ended clock (CK)
  • 1.8 V I/O, 12 bus signals
  • Differential clock (CK, CK#)
  • Chip Select (CS#)
  • 8-bit data bus (DQ[7:0])
  • Read-Write Data Strobe (RWDS)
    • Bidirectional Data Strobe / Mask
    • Output at the start of all transactions to indicate refresh latency
    • Output during read transactions as Read Data Strobe
    • Input during write transactions as Write Data Mask
  • RWDS DCARS Timing
    • During read transactions RWDS is offset by a second clock, phase shifted from CK
    • The Phase Shifted Clock is used to move the RWDS transition edge within the read data eye
• High Performance
  • Up to 333 MBps
  • Double-Data Rate (DDR) - two data transfers per clock
  • 166 MHz clock rate (333 MBps) at 1.8 VCC
  • 100 MHz clock rate (200 MBps) at 3.0 VCC
  • Sequential burst transactions
  • Configurable Burst Characteristics
    • Wrapped burst lengths:
      • 16 bytes (8 clocks)
      • 32 bytes (16 clocks)
      • 64 bytes (32 clocks)
      • 128 bytes (64 clocks)
    • Linear burst
    • Hybrid option - one wrapped burst followed by linear burst
    • Wrapped or linear burst type selected in each transaction
    • Configurable output drive strength
  • Low Power Modes
    • Deep Power Down
  • Package
    • 24-ball FBGA