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Infineon/CYPRESS CY62167ELL-45ZXI product image
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Infineon/CYPRESS CY62167ELL-45ZXIRoHS

Manufacturer
Infineon/CYPRESS
MPN
CY62167ELL-45ZXI
LCSC Part #
C2950509
Packaging
TSOPI-48
Customer #
Key Attributes
16-Mbit Static RAM
Datasheetpdf iconInfineon/CYPRESS CY62167ELL-45ZXI
In-Stock: 10
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QtyUnit PriceTotal Amount
1+$ 14.157$ 14.16
10+$ 12.9536$ 129.54
30+$ 11.8474$ 355.42
100+$ 10.8821$ 1088.21
Standard Packaging480/Full Tray
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory
ManufacturerInfineon/CYPRESS
PackagingTSOPI-48
Operating Temperature-40℃~+85℃
FeaturesAuto power-down function
Memory Size16Mbit
Voltage - Supply4.5V~5.5V
Access Time45ns
Current - Supply-
Standby Supply Current12uA
InterfaceParallel Port (Parallel)
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Introduction

AI Translation

The CY62167E is a high performance CMOS static RAM organized as 1 M words by 16-bits/2 M words by 8-bits. This device features advanced circuit design to provide an ultra low active current. This is ideal for providing More Battery Life (MoBL@) in portable applications. The device also has an automatic power down feature that reduces power consumption when addresses are not toggling. Place the device into standby mode when deselected (CE₁ HIGH, or CE₂ LOW, or both BHE and BLE are HIGH). The input and output pins (I/O₀ through I/O₁₅) are placed in a high impedance state when: ■The device is deselected (CE₁ (overline) HIGH or CE₂ OR (OW)) ■Outputs are disabled (OE HIGH) ■Both byte high enable and byte low enable are disabled (BHE, BLE HIGH) or ■A write operation is in progress (CE₁ (overline) LOW, CE₂ HIGH, and WE LOW)

To write to the device, take chip enables (CE₁ (overline) LOW and CE₂ HIGH) and write enable (WE) input LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O₀ through I/O₇) is written into the location specified on the address pins (A₀ through A₁₉). If byte high enable (BHE) is LOW, then data from the I/O pins (I/O₈ through I/O₁₅) is written into the location specified on the address pins (A₀ through A₁₉).

To read from the device, take chip enables (CE₁ (overline) LOW and CE₂ HIGH) and output enable (OE) LOW while forcing the write enable (WE) HIGH. If byte low enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O₀ to I/O₇. If byte high enable (BHE) is LOW, then data from memory appears on I/O₈ to I/O₁₅. The CY62167E device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels.

Features

AI Translation
  • Configurable as 1M x 16 or as 2M x 8 SRAM
  • Very high speed: 45 ns
  • Wide voltage range: 4.5 V to 5.5 V
  • Ultra low standby power
    • Typical standby current: 1.5 μA
    • Maximum standby current: 12 μA
  • Ultra low active power
    • Typical active current: 2.2 mA at f = 1 MHz
  • Easy memory expansion with CE1 (overline), CE2, and OE (overline) features
  • Automatic power-down when deselected
  • CMOS for optimum speed and power
  • Offered in 48-pin TSOP I package