Infineon/CYPRESS CY7C1460KV33-167AXI

CY7C1460KV33/CY7C1460KVE33/CY7C1462KVE33 are 3.3V, 1M×36 and 2M×18 synchronous pipelined burst SRAMs with No Bus Latency (NoBL) logic. They are designed to support unlimited consecutive read and write operations without wait states. These devices feature advanced NoBL logic that transfers data every clock cycle, enabling continuous read and write operations. This significantly improves data throughput in systems requiring frequent read-write transitions. These devices are pin-compatible and functionally equivalent to Zero Bus Turnaround (ZBT) devices. All synchronous inputs pass through input registers clocked by the rising edge of the clock, and all data outputs pass through output registers clocked by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal; when CEN is deasserted, operation is suspended and the previous clock cycle is extended. Write operations are controlled by byte write select inputs (BW̅a–BW̅d for CY7C1460KV33/CY7C1460KVE33, BW̅a–BW̅b for CY7C1462KVE33) and the Write Enable (WE) input. All write operations are performed through an on-chip synchronous self-timed write circuit. Three synchronous chip enables (CE1̅, CE2, CE3̅) and one asynchronous output enable (OE̅) facilitate memory bank selection and output tristate control. To prevent bus contention, the output drivers are synchronously tristated during the data portion of a write sequence.

• Pin-compatible and functionally equivalent to Zero Bus Turnaround (ZBT)
• 250MHz bus operation with no wait states; available speed grades: 250, 200, and 167MHz
• Internal self-timed output buffer control; no asynchronous OE required
• Fully registered (inputs and outputs) for pipelined operation
• Byte write capability
• 3.3V power supply
• 3.3V/2.5V I/O power supply
• Fast clock-to-output time: 2.5ns for 250MHz devices
• Clock Enable (CEN) pin for operation pause
• Synchronous self-timed write operation
• CY7C1460KV33, CY7C1460KVE33, CY7C1462KVE33 available in JEDEC standard lead-free 100-pin TQFP, lead-free and leaded 165-ball FBGA packages
• IEEE 1149.1 JTAG boundary scan compliant
• Burst capability — linear or interleaved burst order
• "ZZ" sleep mode option
• On-chip Error Correction Code (ECC) for reduced Soft Error Rate (SER)