Infineon/CYPRESS CY9AF341LBPMC-G-JNE2
| Manufacturer | |
| MPN | CY9AF341LBPMC-G-JNE2 |
| LCSC Part # | C2948008 |
| Packaging | LQFP-64 |
| Customer # | |
| Key Attributes | ARM Cortex-M3 32 Bit 40MHz 51 LQFP-64 Microcontrollers RoHS |
| Datasheet | |
| RoHS Compliance | 1 documents available |
| Alternative Parts | 20 |
Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | Infineon/CYPRESS | |
| Packaging | LQFP-64 | |
| ADC (Bit) | 12bit | |
| Operating Temperature | -40℃~+85℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 1.65V~3.6V | |
| Program Storage Size | 96KB | |
| CPU Core | ARM Cortex-M3 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 40MHz | |
| Oscillator Type | Built-in | |
| Number of I/O | 51 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | Infineon/CYPRESS | |
| Packaging | LQFP-64 | |
| ADC (Bit) | 12bit | |
| Operating Temperature | -40℃~+85℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 1.65V~3.6V |
| Type | Description | |
|---|---|---|
| Program Storage Size | 96KB | |
| CPU Core | ARM Cortex-M3 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 40MHz | |
| Oscillator Type | Built-in | |
| Number of I/O | 51 |
Report an ErrorShow similar products (0) >
Introduction
AI Translation
CY9A340NB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, and Communication Interfaces (USB, UART, CSIO, I²C).
Features
AI Translation
- 32-bit ARM Cortex-M3 Core
- Processor version: r2p1
- Up to 40 MHz Frequency Operation
- Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels
- 24-bit System timer (Sys Tick): System timer for OS task management
- On-chip Memories
- [Flash memory]
- Dual Operation Flash memory has the upper bank and the lower bank. This series could implement erase, write and read operations for each bank simultaneously.
- Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank)
- Work area: 32 Kbytes (lower bank)
- Read cycle: 0 wait - cycle Security function for code protection
- [SRAM]
- This Series on - chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I - code bus and D - code bus of Cortex - M3 core. SRAM1 is connected to System bus.
- SRAM0: Up to 16 Kbytes SRAM1: Up to 16 Kbytes
- [Flash memory]
- External Bus Interface
- Supports SRAM, NOR Flash memory device
- Up to 8 chip selects
- 8 -/16 - bit Data width
- Up to 25 - bit Address bit
- Maximum area size: Up to 256 Mbytes
- Supports Address/Data multiplex
- Supports external RDY function
- USB Interface
- [USB device]
- USB2.0 Full - Speed supported
- Max 6 EndPoint supported
- EndPoint 0 is control transfer
- EndPoint 1, 2 can select Bulk - transfer, Interrupt - transfer or Isochronous - transfer
- EndPoint 3 to 5 can select Bulk - transfer or Interrupt - transfer
- EndPoint 1 to 5 is comprised of Double Buffers.
- Endpoint 0, 2 to 5: 64 bytes; Endpoint 1: 256 bytes
- [USB host]
- USB2.0 Full/Low - speed supported
- Bulk - transfer, interrupt - transfer and Isochronous - transfer support
- Automatic detection of connected/disconnected USB Device
- Automatic processing of the IN/OUT token handshake packet
- Max 256 - byte packet - length supported
- Wake - up function supported
- [USB device]
- Multi - function Serial Interface (Max 8 channels)
- 4 channels with 16steps ×9 - bit FIFO (ch.4 to ch.7), 4 channels without FIFO (ch.0 to ch.3)
- Operation mode is selectable from UART, CSIO, I²C for each channel
- [UART]
- Full - duplex double buffer
- Selection with or without parity supported
- Built - in dedicated baud rate generator
- External clock available as a serial clock
- Hardware Flow control (CY9AF341LB, F342LB and F344LB do not support)
- Various error detection functions available (parity errors, framing errors, and overrun errors)
- [CSIO]
- Full - duplex double buffer
- Built - in dedicated baud rate generator
- Overrun error detection function available
- [I²C]
- Standard - mode (Max 100 kbps) / Fast - mode (Max 400 kbps) supported
- DMA Controller (8 channels)
- The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously.
- 8 independently configured and operated channels
- Transfer can be started by software or request from the built - in peripherals
- Transfer address area: 32 - bit (4 Gbytes)
- Transfer mode: Block transfer/Burst transfer/Demand transfer
- Transfer data type: byte/half - word/word
- Transfer block count: 1 to 16
- Number of transfers: 1 to 65536
- A/D Converter (Max 24 channels)
- [12 - bit A/D Converter]
- Successive Approximation type
- Built - in 2 units
- Conversion time: 2.0 μs
- Priority conversion available (priority at 2 levels)
- Scanning conversion mode
- Built - in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps)
- [12 - bit A/D Converter]
- Base Timer (Max 8 channels)
- Operation mode is selectable from 16 - bit PWM timer, 16 - bit PPG timer, 16 -/32 - bit reload timer, 16 -/32 - bit PWC timer for each channel
- General - Purpose I/O Port
- This series can use its pins as general - purpose I/O ports when they are not used for external bus or peripherals.
- Capable of pull - up control per pin
- Capable of reading pin level directly
- Built - in the port relocate function
- Up to 83 fast general - purpose I/O Ports@100 pin Package
- Some ports are 5V tolerant I/O.
- Dual Timer (32 -/16 - bit Down Counter)
- The Dual Timer consists of two programmable 32 -/16 - bit down counters.
- Operation mode is selectable for each channel.
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| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 0.6712 | $ 0.67 |
| 200+ | $ 0.2593 | $ 51.86 |
| 500+ | $ 0.2516 | $ 125.80 |
| 1,190+ | $ 0.2469 | $ 293.81 |
Standard Packaging1190/Full Tray | ||
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Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | Infineon/CYPRESS | |
| Packaging | LQFP-64 | |
| ADC (Bit) | 12bit | |
| Operating Temperature | -40℃~+85℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 1.65V~3.6V | |
| Program Storage Size | 96KB | |
| CPU Core | ARM Cortex-M3 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 40MHz | |
| Oscillator Type | Built-in | |
| Number of I/O | 51 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | Infineon/CYPRESS | |
| Packaging | LQFP-64 | |
| ADC (Bit) | 12bit | |
| Operating Temperature | -40℃~+85℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 1.65V~3.6V |
| Type | Description | |
|---|---|---|
| Program Storage Size | 96KB | |
| CPU Core | ARM Cortex-M3 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 40MHz | |
| Oscillator Type | Built-in | |
| Number of I/O | 51 |
Report an ErrorShow similar products (0) >
Introduction
AI Translation
CY9A340NB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, and Communication Interfaces (USB, UART, CSIO, I²C).
Features
AI Translation
- 32-bit ARM Cortex-M3 Core
- Processor version: r2p1
- Up to 40 MHz Frequency Operation
- Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels
- 24-bit System timer (Sys Tick): System timer for OS task management
- On-chip Memories
- [Flash memory]
- Dual Operation Flash memory has the upper bank and the lower bank. This series could implement erase, write and read operations for each bank simultaneously.
- Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank)
- Work area: 32 Kbytes (lower bank)
- Read cycle: 0 wait - cycle Security function for code protection
- [SRAM]
- This Series on - chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I - code bus and D - code bus of Cortex - M3 core. SRAM1 is connected to System bus.
- SRAM0: Up to 16 Kbytes SRAM1: Up to 16 Kbytes
- [Flash memory]
- External Bus Interface
- Supports SRAM, NOR Flash memory device
- Up to 8 chip selects
- 8 -/16 - bit Data width
- Up to 25 - bit Address bit
- Maximum area size: Up to 256 Mbytes
- Supports Address/Data multiplex
- Supports external RDY function
- USB Interface
- [USB device]
- USB2.0 Full - Speed supported
- Max 6 EndPoint supported
- EndPoint 0 is control transfer
- EndPoint 1, 2 can select Bulk - transfer, Interrupt - transfer or Isochronous - transfer
- EndPoint 3 to 5 can select Bulk - transfer or Interrupt - transfer
- EndPoint 1 to 5 is comprised of Double Buffers.
- Endpoint 0, 2 to 5: 64 bytes; Endpoint 1: 256 bytes
- [USB host]
- USB2.0 Full/Low - speed supported
- Bulk - transfer, interrupt - transfer and Isochronous - transfer support
- Automatic detection of connected/disconnected USB Device
- Automatic processing of the IN/OUT token handshake packet
- Max 256 - byte packet - length supported
- Wake - up function supported
- [USB device]
- Multi - function Serial Interface (Max 8 channels)
- 4 channels with 16steps ×9 - bit FIFO (ch.4 to ch.7), 4 channels without FIFO (ch.0 to ch.3)
- Operation mode is selectable from UART, CSIO, I²C for each channel
- [UART]
- Full - duplex double buffer
- Selection with or without parity supported
- Built - in dedicated baud rate generator
- External clock available as a serial clock
- Hardware Flow control (CY9AF341LB, F342LB and F344LB do not support)
- Various error detection functions available (parity errors, framing errors, and overrun errors)
- [CSIO]
- Full - duplex double buffer
- Built - in dedicated baud rate generator
- Overrun error detection function available
- [I²C]
- Standard - mode (Max 100 kbps) / Fast - mode (Max 400 kbps) supported
- DMA Controller (8 channels)
- The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously.
- 8 independently configured and operated channels
- Transfer can be started by software or request from the built - in peripherals
- Transfer address area: 32 - bit (4 Gbytes)
- Transfer mode: Block transfer/Burst transfer/Demand transfer
- Transfer data type: byte/half - word/word
- Transfer block count: 1 to 16
- Number of transfers: 1 to 65536
- A/D Converter (Max 24 channels)
- [12 - bit A/D Converter]
- Successive Approximation type
- Built - in 2 units
- Conversion time: 2.0 μs
- Priority conversion available (priority at 2 levels)
- Scanning conversion mode
- Built - in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps)
- [12 - bit A/D Converter]
- Base Timer (Max 8 channels)
- Operation mode is selectable from 16 - bit PWM timer, 16 - bit PPG timer, 16 -/32 - bit reload timer, 16 -/32 - bit PWC timer for each channel
- General - Purpose I/O Port
- This series can use its pins as general - purpose I/O ports when they are not used for external bus or peripherals.
- Capable of pull - up control per pin
- Capable of reading pin level directly
- Built - in the port relocate function
- Up to 83 fast general - purpose I/O Ports@100 pin Package
- Some ports are 5V tolerant I/O.
- Dual Timer (32 -/16 - bit Down Counter)
- The Dual Timer consists of two programmable 32 -/16 - bit down counters.
- Operation mode is selectable for each channel.
C2948008 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |
Alternative Parts
| MPN | Manufacturer | Packaging | Availability | Unit Price | ||
|---|---|---|---|---|---|---|
| STM32F103RBT7TR | ST | LQFP-64 | 23 | $ 11.9045 | ||
| CY9AFB41LBPMC-G-JNE2 | Infineon/CYPRESS | LQFP-64 | 0 | $ 0.5756 | ||
| CY9AFB41LBPMC1-G-JNE2 | Infineon/CYPRESS | LQFP-64 | 0 | $ 0.5756 | ||
| CY9AFA41LBPMC-G-JNE2 | Infineon/CYPRESS | LQFP-64 | 0 | $ 0.5756 | ||
| CY9AFA41LBPMC1-G-JNE2 | Infineon/CYPRESS | LQFP-64 | 0 | $ 0.5756 | ||
| CY9AF341LBPMC1-G-JNE2 | Infineon/CYPRESS | LQFP-64 | 0 | $ 0.6712 | ||
| CY9AFB42LBPMC-G-JNE2 | Infineon/CYPRESS | LQFP-64 | 0 | $ 0.5756 | ||
| CY9AFB42LBPMC1-G-JNE2 | Infineon/CYPRESS | LQFP-64 | 0 | $ 0.5756 | ||
| CY9AFA42LBPMC-G-JNE2 | Infineon/CYPRESS | LQFP-64 | 0 | $ 0.5756 | ||
| CY9AFA42LBPMC1-G-JNE2 | Infineon/CYPRESS | LQFP-64 | 0 | $ 0.5756 | ||
| CY9AF342LBPMC-G-JNE2 | Infineon/CYPRESS | LQFP-64 | 0 | $ 0.6712 | ||
| CY9AF342LBPMC1-G-JNE2 | Infineon/CYPRESS | LQFP-64 | 0 | $ 0.6712 | ||
| CY9AF142LBPMC-G-JNE2 | Infineon/CYPRESS | LQFP-64 | 0 | $ 0.5756 | ||
| CY9AF142LBPMC1-G-JNE2 | Infineon/CYPRESS | LQFP-64 | 0 | $ 0.5756 | ||
| CY9AFB44LBPMC-G-JNE2 | Infineon/CYPRESS | LQFP-64 | 0 | $ 0.6712 | ||
| CY9AFB44LBPMC1-G-JNE2 | Infineon/CYPRESS | LQFP-64 | 0 | $ 0.6712 | ||
| CY9AFA44LBPMC-G-JNE2 | Infineon/CYPRESS | LQFP-64 | 0 | $ 0.5756 | ||
| CY9AFA44LBPMC1-G-JNE2 | Infineon/CYPRESS | LQFP-64 | 0 | $ 0.5756 | ||
| CY9AF344LBPMC-G-JNE2 | Infineon/CYPRESS | LQFP-64 | 0 | $ 0.6712 | ||
| CY9AF144LBPMC-G-JNE2 | Infineon/CYPRESS | LQFP-64 | 0 | $ 0.5756 |

