Infineon/CYPRESS CY9BF512RPMC-G-JNE2

The CY9B510R Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the Arm Cortex-M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, CAN, UART, CSIO, I²C, LIN).

• 32-bit Arm Cortex-M3 Core
  • Processor version: r2p1
  • Up to 144 MHz Frequency Operation
  • Memory Protection Unit (MPU): improves the reliability of an embedded system
  • Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels
  • 24-bit System timer (Sys Tick): System timer for OS task management
• On-chip Memories
  • [Flash memory]
    • MainFlash
      • Up to 512 Kbyte
      • Built-in Flash Accelerator System with 16 Kbyte trace buffer memory
      • The read access to Flash memory can be achieved without wait cycle up to operation frequency of 72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System.
      • Security function for code protection
    • WorkFlash
      • 32 Kbyte
      • Read cycle
        • 4wait-cycle: the operation frequency more than 72 MHz
        • 2wait-cycle: the operation frequency more than 40 MHz, and to 72 MHz
        • 0wait-cycle: the operation frequency to 40 MHz
      • Security function is shared with code protection
  • [SRAM]
    • This Series contain a total of up to 64 Kbyte on-chip SRAM. This is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.
    • SRAM0: Up to 32 Kbyte SRAM1: Up to 32 Kbyte
• External Bus Interface
  • Supports SRAM, NOR and NAND Flash device
  • Up to 8 chip selects
  • 8-/16-bit Data width
  • Up to 25-bit Address bit
  • Maximum area size: Up to 256 Mbytes
  • Supports Address/Data multiplex
  • Supports external RDY input
• USB Interface
  • USB interface is composed of Device and Host. PLL for USB is built-in, USB clock can be generated by multiplication of Main clock.
  • USB device
    • USB2.0 Full-Speed supported
    • Max 6 EndPoint supported
      • EndPoint 0 is control transfer
      • EndPoint 1, 2 can be selected Bulk-transfer, Interrupt-transfer or Isochronous-transfer
      • EndPoint 3 to 5 can be selected Bulk-transfer or Interrupt-transfer
      • EndPoint 1 to 5 is comprised Double Buffer
      • The size of each EndPoint is as follows.
        • EndPoint 0, 2 to 5: 64 bytes
        • EndPoint 1: 256 bytes
  • USB host
    • USB2.0 Full/Low-speed supported
    • Bulk-transfer, interrupt-transfer and Isochronous-transfer support
    • USB Device connected/dis-connected automatically detect
    • IN/OUT token handshake packet automatically
    • Max 256-byte packet-length supported
    • Wake-up function supported
• CAN Interface (Max two channels)
  • Compatible with CAN Specification 2.0A/B
  • Maximum transfer rate: 1 Mbps
  • Built-in 32 message buffer
• Multi-function Serial Interface (Max eight channels)
  • 4 channels with 16 steps×9-bit FIFO (ch.4 to ch.7), 4 channels without FIFO (ch.0 to ch.3)
  • Operation mode is selectable from the followings for each channel.
    • UART
      • Full-duplex double buffer
      • Selection with or without parity supported
      • Built-in dedicated baud rate generator
      • External clock available as a serial clock
      • Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)
      • Various error detect functions available (parity errors, framing errors, and overrun errors)
    • CSIO
      • Full-duplex double buffer
      • Built-in dedicated baud rate generator
      • Overrun error detect function available
    • LIN
      • LIN protocol Rev.2.1 supported
      • Full-duplex double buffer
      • Master/Slave mode supported
      • LIN break field generate (can be changed 13 to 16-bit length)
      • LIN break delimiter generate (can be changed 1 to 4-bit length)
      • Various error detect functions available (parity errors, framing errors, and overrun errors)
    • I2C
      • Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported
• DMA Controller (Eight channels)
  • DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.
  • 8 independently configured and operated channels
  • Transfer can be started by software or request from the built-in peripherals
  • Transfer address area: 32-bit (4 Gbyte)
  • Transfer mode: Block transfer/Burst transfer/Demand transfer
  • Transfer data type: byte/half-word/word
  • Transfer block count: 1 to 16
  • Number of transfers: 1 to 65536
• A/D Converter (Max 16 channels)
  • 12-bit A/D Converter
    • Successive Approximation Register type
    • Built-in 3 unit
    • Conversion time: 1.0 μs @ 5 V
    • Priority conversion available (priority at 2 levels)
    • Scanning conversion mode
    • Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps)
• Base Timer (Max eight channels)
  • Operation mode is selectable from the followings for each channel.
    • 16-bit PWM timer
    • 16-bit PPG timer
    • 16-/32-bit