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Infineon/CYPRESS S25FL512SDPMFVG10 product image
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Infineon/CYPRESS S25FL512SDPMFVG10RoHS

Manufacturer
Infineon/CYPRESS
MPN
S25FL512SDPMFVG10
LCSC Part #
C2944627
Packaging
SOIC-16
Customer #
Key Attributes
512Mbit 2.7V~3.6V 133MHz SPI SOIC-16 Memory RoHS
Datasheetpdf iconInfineon/CYPRESS S25FL512SDPMFVG10
In-Stock: 24
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Minimum: 1Multiple: 1Sales Unit: Piece
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QtyUnit PriceTotal Amount
1+$ 16.0226$ 16.02
10+$ 15.272$ 152.72
30+$ 13.9703$ 419.11
100+$ 12.8356$ 1283.56
Standard Packaging480/Full Tray
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory
ManufacturerInfineon/CYPRESS
PackagingSOIC-16
Operating Temperature-40℃~+85℃
FeaturesWrite enable latch;Power-on reset;Hardware write protection;Software write protection;ECC error correction
Memory Size512Mbit
Voltage - Supply2.7V~3.6V
Program / Erase Cycles100,000 cycles
Clock Frequency133MHz
Data Retention - TDR (Year)20 Years
Block Erase Time(tBE)-
Write Cycle Time(tWC)-
Page Programming Time (Tpp)340us
Standby Supply Current70uA
InterfaceSPI
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Introduction

AI Translation

The Infineon S25FL512S device is a flash non-volatile memory product using:

  • MirrorBit™ technology - that stores two data bits in each memory array transistor
  • Eclipse architecture - that dramatically improves program and erase performance
  • 65 nm process lithography

Features

AI Translation
  • CMOS 3.0 V Core with versatile I/O
  • SPI with Multi-I/O
  • Density - 512 Mb (64 MB)
  • SPI - SPI Clock polarity and phase modes 0 and 3 - DDR option - Extended Addressing: 32-bit address - Serial Command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families - Multi I/O Command set and footprint compatible with the S25FL-P SPI family
  • READ Commands - Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR - AutoBoot - power up or reset and execute a Normal or Quad read command automatically at a preselected address - Common Flash Interface (CFI) data for configuration information
  • Programming (1.5 MBps) - 512-byte Page Programming buffer - Quad-Input Page Programming (QPP) for slow clock systems - Automatic ECC - internal hardware Error Correction Code generation with single bit error correction
  • Erase (0.5 to 0.65 MBps) - Uniform 256-KB sectors Cycling Endurance - 100,000 Program-Erase Cycles, minimum
  • Data Retention - 20-Year Data Retention, minimum
  • Security Features - OTP array of 1024 bytes - Block Protection: • Status Register bits to control protection against program or erase of a contiguous range of sectors. • Hardware and software control options - Advanced Sector Protection (ASP) • Individual sector protection controlled by boot code or password
  • Infineon 65 nm MirrorBit Technology with Eclipse Architecture
  • Temperature range: - Industrial -40 ℃ to +85 ℃
  • Industrial Plus -40 ℃ to +105 ℃
  • Automotive, AEC-Q100 Grade 3 -40 ℃ to +85 ℃
  • Automotive, AEC-Q100 Grade 2 -40 ℃ to +105 ℃
  • Automotive, AEC-Q100 Grade 1 -40 ℃ to +125 ℃
  • Packages (all Pb-free) - 16-pin SOIC (300 mil) - 24-BGA (6x8 mm) - 5x5 ball (FAB024) and 4x6 ball (FAC024) footprint options - Known Good Die and Known Tested Die