TI TPS659114A2NMAR

The TPS65911 is an integrated PMIC in a 98-pin 0.65mm pitch BGA package. It is designed for applications powered by a single Li-ion or Li-ion polymer battery, 3 series-connected NiMH cells, or a 5V input, as well as applications requiring multiple power rails. The device provides 3 buck converters, 1 controller for an external FET (to support high-current rails), and 8 LDOs, specifically designed as a flexible PMIC to support various processors and applications. Two of the buck converters power dual processor cores and support dynamic voltage scaling via a dedicated I2C interface for optimal power savings. The third converter supplies I/O and memory in the system. The device includes 8 general-purpose LDO regulators offering a wide range of voltage and current capabilities. Five of the LDOs support 1 to 3.3V (in 100mV steps), while the other three (LDO1, LDO2, LDO4) support 1.0 to 3.3V (in 50mV steps). All LDO regulators are fully controlled via the I2C interface. In addition to power management, the device includes an EPC to manage system power sequencing and an RTC. Power sequencing is configured by EEPROM.

• Embedded Power Controller (EPC) with EEPROM programmability
• 2 high-efficiency step-down DC/DC converters for processor cores (VDD1, VDD2)
• 1 high-efficiency step-down DC/DC converter for I/O power supply (VIO)
• 1 controller for external FET (VDDCtrl)
• Dynamic Voltage Scaling (DVS) for processor cores
• 8 Low Drop-Out (LDO) voltage regulators and 1 RTC LDO (powering internal RTC)
• 1 high-speed I2C interface for general control commands (CTL-I2C)
• 2 independent enable signals for power resource control (EN1, EN2) – alternatively, EN1 and EN2 pins can be used as high-speed I2C interfaces (dedicated voltage scaling for VDD1 and VDD2)
• Thermal shutdown protection and thermal module detection
• 1 RTC resource featuring: 32.768kHz crystal oscillator or 32kHz built-in RC oscillator, date/time/calendar – alarm function
• 9 configurable GPIO interfaces with multiplexing capability: 4 usable as enable signals for external resources, included in power-up sequence, controlled by state machine; as GPI, GPIO supports logic level detection and can generate maskable interrupts for wake-up – 2 of the GPIOs feature 10mA sink current capability for LED driving
• DC/DC converter switching synchronization via 1 external 3MHz clock
• 2 reset inputs: cold reset (HDRST) – power initialization reset for warm reset input (PWRDN)
• 32kHz clock and reset (NRESPWRON) for system, plus additional reset signal outputs
• Watchdog
• 2 switched LED pulse generators and 1 PWM generator
• 2 comparators for system control, connected to VCCS pin
• JTAG and boundary scan (not accessible in functional mode [test purposes])

• Portable and handheld systems