TI TMS320DM643AGNZ5

The TMS320C64x™ DSPs (including the TMS320DM643 device) are the highest - performance fixed - point DSP generation in the TMS320C6000™ DSP platform. The TMS320DM643 (DM643) device is based on the second - generation high - performance, advanced VelociTI™ very - long - instruction - word (VLIW) architecture (VelociTI.2™), making these DSPs an excellent choice for digital media applications. The C64x™ is a code - compatible member of the C6000™ DSP platform. With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the DM643 device offers cost - effective solutions to high - performance DSP programming challenges. The DM643 DSP possesses the operational flexibility of high - speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general - purpose registers of 32 - bit word length and eight highly independent functional units—two multipliers for a 32 - bit result and six arithmetic logic units (ALUs)—with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™ architecture. The DM643 can produce four 16 - bit multiply - accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8 - bit MACs per cycle for a total of 4800 MMACS. The DM643 DSP also has application - specific hardware logic, on - chip memory, and additional on - chip peripherals similar to the other C6000™ DSP platform devices. The DM643 uses a two - level cache - based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128 - Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128 - Kbit 2 - way set - associative cache. The Level 2 memory/cache (L2) consists of an 2 - Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: two configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter - integrated circuit (I2C) Bus module; one multichannel buffered serial port (McBSP); three 32 - bit general - purpose timers; a user - configurable 16 - bit or 32 - bit host - port interface (HPI16/HPI32); a 16 - pin general - purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64 - bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals. The DM643 device has two configurable video port peripherals (VP1 and VP2). These video port peripherals provide a glueless interface to common.

• High - Performance Digital Media Processor
• 2 - , 1.67 - ns Instruction Cycle Time
• 500 - , 600 - MHz Clock Rate
• Eight 32 - Bit Instructions/Cycle
• 4000, 4800 MIPS
• Fully Software - Compatible With C64x™
• VelociTI.2™ Extensions to VelociTI™ Advanced Very - Long - Instruction - Word (VLIW) TMS320C64x™ DSP Core
• Eight Highly Independent Functional Units With VelociTI.2™ Extensions
• Six ALUs (32 - /40 - Bit), Each Supports Single 32 - Bit, Dual 16 - Bit, or Quad 8 - Bit Arithmetic per Clock Cycle
• Two Multipliers Support Four 16×16 - Bit Multiplies (32 - Bit Results) per Clock Cycle or Eight 8×8 - Bit Multiplies (16 - Bit Results) per Clock Cycle
• Load - Store Architecture With Non - Aligned Support
• 64 32 - Bit General - Purpose Registers
• Instruction Packing Reduces Code Size
• All Instructions Conditional
• Instruction Set Features
• Byte - Addressable (8 - /16 - /32 - /64 - Bit Data)
• 8 - Bit Overflow Protection
• Bit - Field Extract, Set, Clear
• Normalization, Saturation, Bit - Counting
• VelociTI.2™ Increased Orthogonality
• L1/L2 Memory Architecture
• 128K - Bit (16K - Byte) L1P Program Cache (Direct Mapped)
• 128K - Bit (16K - Byte) L1D Data Cache (2 - Way Set - Associative)
• 2M - Bit (256K - Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
• Endianess: Little Endian, Big Endian
• 64 - Bit External Memory Interface (EMIF)
• Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
• 1024M - Byte Total Addressable External Memory Space
• Enhanced Direct - Memory - Access (EDMA) Controller (64 Independent Channels)
• 10/100 Mb/s Ethernet MAC (EMAC)
• IEEE 802.3 Compliant
• Media Independent Interface (MII)
• 8 Independent Transmit (TX) Channels and 1 Receive (RX) Channel
• Management Data Input/Output (MDIO)
• Two Configurable Video Ports (VP1, VP2)
• Providing a Glueless I/F to Common Video Decoder and Encoder Devices
• Supports Multiple Resolutions/Video Stds
• VCXO Interpolated Control Port (VIC)
• Supports Audio/Video Synchronization
• Host - Port Interface (HPI) [32 - /16 - Bit]
• Multichannel Audio Serial Port (McASP)
• Eight Serial Data Pins
• Wide Variety of I²S and Similar Bit Stream Format
• Integrated Digital Audio I/F Transmitter Supports S/PDIF, IEC60958 - 1, AES - 3, CP - 430 Formats
• Inter - Integrated Circuit (I²C Bus™)
• Multichannel Buffered Serial Port
• CLKS Input Not Supported
• Three 32 - Bit General - Purpose Timers
• Sixteen General - Purpose I/O (GPIO) Pins
• Flexible PLL Clock Generator
• IEEE - 1149.1 (JTAG) BoundaryScan - Compatible
• 548 - Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8 - mm Ball Pitch
• 548 - Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0 - mm Ball Pitch
• 0.13 - μm/6 - Level Cu Metal Process (CMOS)
• 3.3 - V I/O, 1.2 - V Internal (- 500)
• 3.3 - V I/O, 1.4 - V Internal (- 600)