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Nexperia 74LVC16373ADGG,118 product image
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Nexperia 74LVC16373ADGG,118RoHS

Manufacturer
Nexperia
MPN
74LVC16373ADGG,118
LCSC Part #
C282344
Packaging
TSSOP-48-6.2mm
Customer #
Key Attributes
16-bit D-type transparent latch with 5V-tolerant inputs/outputs and 3-state function
Datasheetpdf iconNexperia 74LVC16373ADGG,118
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10+$ 0.6294$ 6.29
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500+$ 0.4202$ 210.10
1,000+$ 0.3958$ 395.80
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Latches
ManufacturerNexperia
PackagingTSSOP-48-6.2mm
Quiescent Current0.1uA
Series74LVC
Logic TypeD Latch
Voltage - Supply2.7V~3.6V
Current - Output Low(IOL)-
Operating Temperature-40℃~+125℃
Output TypeTri-State
Current - Output High(IOH)-
Setup Time1ns
Number of Gates2
Hold Time0.9ns
Propagation Delay2.4ns
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Introduction

AI Translation

The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches with 3-state outputs. The devices can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The devices feature two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When nLE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Bus hold on the data inputs eliminates the need for external pull-up resistors to hold unused inputs.

Features

AI Translation
  • Overvoltage tolerant inputs to 5.5 V
  • Wide supply voltage range from 1.2 V to 3.6 V
  • CMOS low power dissipation
  • MULTIBYTE flow-through standard pinout architecture
  • Multiple low inductance supply pins for minimum noise and ground bounce
  • Direct interface with TTL levels
  • All data inputs have bus hold (74LVCH16373A only)
  • IOFF circuitry provides partial Power-down mode operation
  • Complies with JEDEC standards: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V)
  • ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃

Applications

AI Translation
  • Converter for mixed 3.3V and 5V environments