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Infineon/CYPRESS CY7C1069G30-10ZSXI product image
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Infineon/CYPRESS CY7C1069G30-10ZSXIRoHS

Manufacturer
Infineon/CYPRESS
MPN
CY7C1069G30-10ZSXI
LCSC Part #
C2759942
Packaging
TSOPII-54-10.2mm
Customer #
Key Attributes
16-Mbit Static RAM with Error-Correcting Code (ECC)
Datasheetpdf iconInfineon/CYPRESS CY7C1069G30-10ZSXI
In-Stock: 10
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1+$ 40.3178$ 21.7717$ 21.77
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory
ManufacturerInfineon/CYPRESS
PackagingTSOPII-54-10.2mm
Operating Temperature-40℃~+85℃
FeaturesBuilt-in ECC function;Auto power-down function
Memory Size16Mbit
Voltage - Supply2.2V~3.6V
Access Time10ns
Current - Supply90mA
InterfaceParallel Port (Parallel)
Standby Supply Current30mA
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Introduction

AI Translation

The CY7C1069G and CY7C1069GE are dual chip enable high-performance CMOS fast static RAM devices with embedded ECC. The CY7C1069G device is available in standard pin configurations. The CY7C1069GE device includes a single bit error indication pin (ERR) that signals the host processor in the case of an ECC error-detection and correction event.

To write to the device, take Chip Enables (CE1(overline) LOW and CE2 HIGH) and Write Enable (WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins A0 through A20.

To read from the device, take Chip 2 enables (CE1(overline) LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).

On CY7C1069GE devices, the detection and correction of a single-bit error in the accessed location is indicated by the assertion of the ERR output (ERR = High).

All I/Os (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), and control signals are de-asserted (CE1 / CE2 OE, WE). CY7C1069G and CY7C1069GE devices are available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout, and in a 48-ball VFBGA package.

Features

AI Translation
  • High speed
  • tAA = 10 ns
  • Embedded error-correcting code (ECC) for single-bit error correction
  • Low active and standby currents
  • ICC = 90 mA typical at 100 MHz
  • ISB2 = 20 mA typical
  • Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V
  • 1.0-V data retention
  • Transistor-transistor logic (TTL) compatible inputs and outputs
  • ERR pin to indicate 1-bit error detection and correction
  • Available in Pb-free 54-pin TSOP II, and 48-ball VFBGA packages