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TI SN74AHC16373DGGR
| Manufacturer | |
| MPN | SN74AHC16373DGGR |
| LCSC Part # | C2675287 |
| Packaging | TSSOP-48-6.1mm |
| Customer # | |
| Key Attributes | 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| Datasheet |  TI SN74AHC16373DGGR |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Latches | |
| Manufacturer | TI | |
| Packaging | TSSOP-48-6.1mm | |
| Quiescent Current | 40uA | |
| Series | 74AHC | |
| Logic Type | D Latch | |
| Voltage - Supply | 2V~5.5V | |
| Operating Temperature | -40℃~+85℃ | |
| Current - Output Low(IOL) | 8mA | |
| Output Type | Tri-State | |
| Setup Time | 4ns | |
| Number of Gates | 16 | |
| Current - Output High(IOH) | 8mA | |
| Hold Time | 1ns | |
| Propagation Delay | 1ns |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Latches | |
| Manufacturer | TI | |
| Packaging | TSSOP-48-6.1mm | |
| Quiescent Current | 40uA | |
| Series | 74AHC | |
| Logic Type | D Latch | |
| Voltage - Supply | 2V~5.5V | |
| Operating Temperature | -40℃~+85℃ |
| Type | Description | |
|---|---|---|
| Current - Output Low(IOL) | 8mA | |
| Output Type | Tri-State | |
| Setup Time | 4ns | |
| Number of Gates | 16 | |
| Current - Output High(IOH) | 8mA | |
| Hold Time | 1ns | |
| Propagation Delay | 1ns |
Introduction
The ’AHC16373 devices are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels at the D inputs.
A buffered output-enable (OE(overline)) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
To ensure the high-impedance state during power up or power down, OE(overline) should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN74AHC16373 is characterized for operation from -40℃ to 85℃.
Features
- Operating Range 2-V to 5.5V VCC
- Distributed VCC and GND Pins Minimize High-Speed Switching Noise
- Flow-Through Architecture Optimizes PCB Layout
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model ΔC = 200 pF, R = 0
- Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
Applications
- Buffer register implementation
- I/O port implementation
- Bidirectional bus driver implementation
- Working register implementation
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 1.3574 | $ 1.36 |
| 10+ | $ 1.1112 | $ 11.11 |
| 30+ | $ 0.9754 | $ 29.26 |
| 100+ | $ 0.8239 | $ 82.39 |
| 500+ | $ 0.756 | $ 378.00 |
| 1,000+ | $ 0.7245 | $ 724.50 |
Standard Packaging2000/Full Reel | ||
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Latches | |
| Manufacturer | TI | |
| Packaging | TSSOP-48-6.1mm | |
| Quiescent Current | 40uA | |
| Series | 74AHC | |
| Logic Type | D Latch | |
| Voltage - Supply | 2V~5.5V | |
| Operating Temperature | -40℃~+85℃ | |
| Current - Output Low(IOL) | 8mA | |
| Output Type | Tri-State | |
| Setup Time | 4ns | |
| Number of Gates | 16 | |
| Current - Output High(IOH) | 8mA | |
| Hold Time | 1ns | |
| Propagation Delay | 1ns |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Latches | |
| Manufacturer | TI | |
| Packaging | TSSOP-48-6.1mm | |
| Quiescent Current | 40uA | |
| Series | 74AHC | |
| Logic Type | D Latch | |
| Voltage - Supply | 2V~5.5V | |
| Operating Temperature | -40℃~+85℃ |
| Type | Description | |
|---|---|---|
| Current - Output Low(IOL) | 8mA | |
| Output Type | Tri-State | |
| Setup Time | 4ns | |
| Number of Gates | 16 | |
| Current - Output High(IOH) | 8mA | |
| Hold Time | 1ns | |
| Propagation Delay | 1ns |
Introduction
The ’AHC16373 devices are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels at the D inputs.
A buffered output-enable (OE(overline)) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
To ensure the high-impedance state during power up or power down, OE(overline) should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN74AHC16373 is characterized for operation from -40℃ to 85℃.
Features
- Operating Range 2-V to 5.5V VCC
- Distributed VCC and GND Pins Minimize High-Speed Switching Noise
- Flow-Through Architecture Optimizes PCB Layout
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model ΔC = 200 pF, R = 0
- Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
Applications
- Buffer register implementation
- I/O port implementation
- Bidirectional bus driver implementation
- Working register implementation
C2675287 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |