- Pinout Diagram
- Footprint Diagram
Infineon/CYPRESS CY7C68013A-56PVXC
| Manufacturer | |
| MPN | CY7C68013A-56PVXC |
| LCSC Part # | C26717 |
| Packaging | SSOP-56-300mil |
| Customer # | |
| Key Attributes | EZ-USB FX2LP USB Microcontroller, High-Speed USB Peripheral Controller |
| Datasheet |  Infineon/CYPRESS CY7C68013A-56PVXC |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | Infineon/CYPRESS | |
| Packaging | SSOP-56-300mil | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 3V~3.6V | |
| CPU Core | 51 Family | |
| Core Size | 8 Bit | |
| CPU Maximum Speed | 48MHz | |
| Number of I/O | 24 |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 26 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
Cypress’s EZ-USB FX2LP (CY7C68013A/14A) is a low power version of the EZ-USB FX2 (CY7C68013), which is a highly integrated, low power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a cost effective solution that provides superior time-to-market advantages with low power to enable bus powered applications. The ingenious architecture of FX2LP results in data transfer rates of over 53 Mbytes per second, the maximum allowable USB 2.0 bandwidth, while still using a low cost 8051 microcontroller in a package as small as a 56 VFBGA (5 mm×5 mm). Because it incorporates the USB 2.0 transceiver, the FX2LP is more economical, providing a smaller footprint solution than USB 2.0 SIE or external transceiver implementations. With EZ-USB FX2LP, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded microcontroller for application specific functions and decreasing development time to ensure USB compatibility. The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8-bit or 16-bit data bus) provides an easy and glueless interface to popular interfaces such as ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors. The FX2LP draws less current than the FX2 (CY7C68013), has double the on-chip code/data RAM, and is fit, form and function compatible with the 56, 100, and 128 pin FX2.
Features
- USB 2.0 USB IF high speed certified (TID # 40460272)
- Single chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor
- Fit, form, and function compatible with the FX2
- Pin compatible
- Object code compatible
- Functionally compatible (FX2LP is a superset)
- Ultra low power: ICC No more than 85 mA in any mode
- Ideal for bus and battery powered applications
- Software: 8051 code runs from:
- Internal RAM, which is downloaded through USB
- Internal RAM, which is loaded from EEPROM
- External memory device (128 pin package)
- 16 KB of on-chip code/data RAM
- Four programmable BULK, INTERRUPT, and ISOCHRONOUS endpoints
- Buffering options: Double, triple, and quad
- Additional programmable (BULK/INTERRUPT) 64-byte endpoint
- 8-bit or 16-bit external data interface
- Smart media standard ECC generation
- GPIF (general programmable interface)
- Enables direct connection to most parallel interfaces
- Programmable waveform descriptors and configuration registers to define waveforms
- Supports multiple ready (RDY) inputs and Control (CTL) outputs
- Integrated, industry standard enhanced 8051
- 48 MHz, 24 MHz, or 12 MHz CPU operation
- Four clocks per instruction cycle
- Two USARTs
- Three counter/timers
- Expanded interrupt system
- Two data pointers
- 3.3 V operation with 5 V tolerant inputs
- Vectored USB interrupts and GPIF/FIFO interrupts
- Separate data buffers for the setup and data portions of a CONTROL transfer
- Integrated I2C controller, runs at 100 or 400 kHz
- Four integrated FIFOs
- Integrated glue logic and FIFOs lower system cost
- Automatic conversion to and from 16-bit buses
- Master or slave operation
- Uses external clock or asynchronous strobes
- Easy interface to ASIC and DSP ICs
- Available in commercial and industrial temperature grade (all packages except VFBGA)
- CY7C68014A: Ideal for Battery Powered Applications
- Suspend current: 100 μA (typ)
- CY7C68013A: Ideal for Non Battery Powered Applications
- Suspend current: 300 μA (typ)
- Available in Five Pb-free Packages with Up to 40 GPIOs
- 128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs), 56-pin QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin VFBGA (24 GPIOs)
- CY7C68016A: Ideal for Battery Powered Applications
- Suspend current: 100 μA (typ)
- CY7C68015A: Ideal for Non Battery Powered Applications
- Suspend current: 300 μA (typ)
- Available in Pb-free 56-pin QFN Package (26 GPIOs)
- Two more GPIOs than CY7C68013A/14A enabling additional features in same footprint
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 14.1296 | $ 14.13 |
| 10+ | $ 12.3079 | $ 123.08 |
| 26+ | $ 11.197 | $ 291.12 |
| 104+ | $ 10.2667 | $ 1067.74 |
Standard Packaging26/Full Tube | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | Infineon/CYPRESS | |
| Packaging | SSOP-56-300mil | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 3V~3.6V | |
| CPU Core | 51 Family | |
| Core Size | 8 Bit | |
| CPU Maximum Speed | 48MHz | |
| Number of I/O | 24 |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 26 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
Cypress’s EZ-USB FX2LP (CY7C68013A/14A) is a low power version of the EZ-USB FX2 (CY7C68013), which is a highly integrated, low power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a cost effective solution that provides superior time-to-market advantages with low power to enable bus powered applications. The ingenious architecture of FX2LP results in data transfer rates of over 53 Mbytes per second, the maximum allowable USB 2.0 bandwidth, while still using a low cost 8051 microcontroller in a package as small as a 56 VFBGA (5 mm×5 mm). Because it incorporates the USB 2.0 transceiver, the FX2LP is more economical, providing a smaller footprint solution than USB 2.0 SIE or external transceiver implementations. With EZ-USB FX2LP, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded microcontroller for application specific functions and decreasing development time to ensure USB compatibility. The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8-bit or 16-bit data bus) provides an easy and glueless interface to popular interfaces such as ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors. The FX2LP draws less current than the FX2 (CY7C68013), has double the on-chip code/data RAM, and is fit, form and function compatible with the 56, 100, and 128 pin FX2.
Features
- USB 2.0 USB IF high speed certified (TID # 40460272)
- Single chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor
- Fit, form, and function compatible with the FX2
- Pin compatible
- Object code compatible
- Functionally compatible (FX2LP is a superset)
- Ultra low power: ICC No more than 85 mA in any mode
- Ideal for bus and battery powered applications
- Software: 8051 code runs from:
- Internal RAM, which is downloaded through USB
- Internal RAM, which is loaded from EEPROM
- External memory device (128 pin package)
- 16 KB of on-chip code/data RAM
- Four programmable BULK, INTERRUPT, and ISOCHRONOUS endpoints
- Buffering options: Double, triple, and quad
- Additional programmable (BULK/INTERRUPT) 64-byte endpoint
- 8-bit or 16-bit external data interface
- Smart media standard ECC generation
- GPIF (general programmable interface)
- Enables direct connection to most parallel interfaces
- Programmable waveform descriptors and configuration registers to define waveforms
- Supports multiple ready (RDY) inputs and Control (CTL) outputs
- Integrated, industry standard enhanced 8051
- 48 MHz, 24 MHz, or 12 MHz CPU operation
- Four clocks per instruction cycle
- Two USARTs
- Three counter/timers
- Expanded interrupt system
- Two data pointers
- 3.3 V operation with 5 V tolerant inputs
- Vectored USB interrupts and GPIF/FIFO interrupts
- Separate data buffers for the setup and data portions of a CONTROL transfer
- Integrated I2C controller, runs at 100 or 400 kHz
- Four integrated FIFOs
- Integrated glue logic and FIFOs lower system cost
- Automatic conversion to and from 16-bit buses
- Master or slave operation
- Uses external clock or asynchronous strobes
- Easy interface to ASIC and DSP ICs
- Available in commercial and industrial temperature grade (all packages except VFBGA)
- CY7C68014A: Ideal for Battery Powered Applications
- Suspend current: 100 μA (typ)
- CY7C68013A: Ideal for Non Battery Powered Applications
- Suspend current: 300 μA (typ)
- Available in Five Pb-free Packages with Up to 40 GPIOs
- 128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs), 56-pin QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin VFBGA (24 GPIOs)
- CY7C68016A: Ideal for Battery Powered Applications
- Suspend current: 100 μA (typ)
- CY7C68015A: Ideal for Non Battery Powered Applications
- Suspend current: 300 μA (typ)
- Available in Pb-free 56-pin QFN Package (26 GPIOs)
- Two more GPIOs than CY7C68013A/14A enabling additional features in same footprint
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991A3 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991A3 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |