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EDA ModelsEasyEDA
TI CD4020BPWR
| Manufacturer | |
| MPN | CD4020BPWR |
| LCSC Part # | C2652987 |
| Packaging | TSSOP-16 |
| Customer # | |
| Key Attributes | CMOS Ripple-Carry Binary Counter/Dividers |
| Datasheet |  TI CD4020BPWR |
Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Manufacturer | TI | |
| Packaging | TSSOP-16 | |
| Logic Family | - | |
| Voltage - Supply | 3V~18V | |
| Direction | Up Counter | |
| Trigger Type | Falling Edge | |
| Timing | - | |
| Operating Temperature | -55℃~+125℃ | |
| Reset | Asynchronous | |
| Number of Elements | 1 | |
| Propagation Delay | 65ns | |
| Count Rate | 12MHz | |
| Features | Reset function |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Manufacturer | TI | |
| Packaging | TSSOP-16 | |
| Logic Family | - | |
| Voltage - Supply | 3V~18V | |
| Direction | Up Counter | |
| Trigger Type | Falling Edge |
| Type | Description | |
|---|---|---|
| Timing | - | |
| Operating Temperature | -55℃~+125℃ | |
| Reset | Asynchronous | |
| Number of Elements | 1 | |
| Propagation Delay | 65ns | |
| Count Rate | 12MHz | |
| Features | Reset function |
Report an ErrorShow similar products (0) >
Introduction
AI Translation
CD4020B, CD4024B, and CD4040B are ripple-carry binary counters. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times. All inputs and outputs are buffered.
Features
AI Translation
- Medium-speed operation
- Fully static operation
- Buffered inputs and outputs
- 100% tested for quiescent current at 20x
- Standardized, symmetrical output characteristics
- Common reset
- 5-V, 10-V, and 15-V parametric ratings
- Maximum input current of ±1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25℃
- Noise margin (over full package-temperature range): 1 V at VDD = 5 V; 2 V at VDD = 10 V; 2.5 V at VDD = 15 V
- Meets all requirements of JEDEC Tentative Standard No. 138, "Standard Specifications for Description of 'B' Series CMOS Devices"
Applications
AI Translation
- Control counters
- Frequency dividers
- Time-delay circuits
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| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 0.58 | $ 0.58 |
| 10+ | $ 0.4696 | $ 4.70 |
| 30+ | $ 0.4143 | $ 12.43 |
| 100+ | $ 0.3591 | $ 35.91 |
| 500+ | $ 0.3266 | $ 163.30 |
| 1,000+ | $ 0.2746 | $ 274.60 |
Standard Packaging2000/Full Reel | ||
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Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Manufacturer | TI | |
| Packaging | TSSOP-16 | |
| Logic Family | - | |
| Voltage - Supply | 3V~18V | |
| Direction | Up Counter | |
| Trigger Type | Falling Edge | |
| Timing | - | |
| Operating Temperature | -55℃~+125℃ | |
| Reset | Asynchronous | |
| Number of Elements | 1 | |
| Propagation Delay | 65ns | |
| Count Rate | 12MHz | |
| Features | Reset function |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Counters, Dividers | |
| Manufacturer | TI | |
| Packaging | TSSOP-16 | |
| Logic Family | - | |
| Voltage - Supply | 3V~18V | |
| Direction | Up Counter | |
| Trigger Type | Falling Edge |
| Type | Description | |
|---|---|---|
| Timing | - | |
| Operating Temperature | -55℃~+125℃ | |
| Reset | Asynchronous | |
| Number of Elements | 1 | |
| Propagation Delay | 65ns | |
| Count Rate | 12MHz | |
| Features | Reset function |
Report an ErrorShow similar products (0) >
Introduction
AI Translation
CD4020B, CD4024B, and CD4040B are ripple-carry binary counters. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times. All inputs and outputs are buffered.
Features
AI Translation
- Medium-speed operation
- Fully static operation
- Buffered inputs and outputs
- 100% tested for quiescent current at 20x
- Standardized, symmetrical output characteristics
- Common reset
- 5-V, 10-V, and 15-V parametric ratings
- Maximum input current of ±1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25℃
- Noise margin (over full package-temperature range): 1 V at VDD = 5 V; 2 V at VDD = 10 V; 2.5 V at VDD = 15 V
- Meets all requirements of JEDEC Tentative Standard No. 138, "Standard Specifications for Description of 'B' Series CMOS Devices"
Applications
AI Translation
- Control counters
- Frequency dividers
- Time-delay circuits
C2652987 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |