Hangzhou Ruimeng Tech MS90C385B
| Manufacturer | Hangzhou Ruimeng TechAsian Brands |
| MPN | MS90C385B |
| LCSC Part # | C231930 |
| Packaging | TSSOP-56-6.1mm |
| Customer # | |
| Key Attributes | MS90C385B - +3.3V 150MHz 24-bit Flat Panel Display (FPD) LVDS Signal Transmitter |
| Datasheet |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Drivers, Receivers, Transceivers | |
| Manufacturer | Hangzhou Ruimeng Tech | |
| Packaging | TSSOP-56-6.1mm | |
| Voltage - Supply | 3.3V | |
| Type | Driver | |
| Data Rate | 1.05Gbps | |
| Number of Drivers | 4 | |
| Features | Low power standby / automatic shutdown on failure;Configurable output swing | |
| Level Standard | LVDS;TTL | |
| Number of Receivers | 0 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Drivers, Receivers, Transceivers | |
| Manufacturer | Hangzhou Ruimeng Tech | |
| Packaging | TSSOP-56-6.1mm | |
| Voltage - Supply | 3.3V | |
| Type | Driver |
| Type | Description | |
|---|---|---|
| Data Rate | 1.05Gbps | |
| Number of Drivers | 4 | |
| Features | Low power standby / automatic shutdown on failure;Configurable output swing | |
| Level Standard | LVDS;TTL | |
| Number of Receivers | 0 |
Introduction
The MS90C385B converts 28-bit TTL data into 4-channel LVDS signals. The clock channel is phase-locked and output in parallel with the data channels. At a clock frequency of 150MHz, 24-bit RGB data, 3-bit LCD timing data, and 1-bit control data are transmitted at 1050Mbps per LVDS data channel. At an input clock frequency of 150MHz, the data transfer rate is 525Mbytes/sec. This device is an ideal solution for addressing EMI and cable length issues associated with high-bandwidth, high-speed TTL signal interfaces.
Features
- Frequency range: 20 - 150MHz clock signal
- Reduced bus minimizes wiring size and cost
- Core supply voltage: 3.3V
- I/O supply voltage: 1.8V / 3.3V compatible
- Low-power mode
- Supports VGA, SVGA, XGA, SXGA
- Supports spread spectrum clock generation
- Integrated input jitter filter
- 525 Megabytes/sec bandwidth
- Reduced LVDS swing for lower EMI (200mV or 345mV LVDS swing selectable)
- PLL requires no external components
- Compliant with TIA/EIA-644 LVDS standard
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 1.3983 | $ 1.40 |
| 10+ | $ 1.1948 | $ 11.95 |
| 30+ | $ 1.0834 | $ 32.50 |
| 100+ | $ 0.9575 | $ 95.75 |
| 500+ | $ 0.7524 | $ 376.20 |
| 1,000+ | $ 0.7266 | $ 726.60 |
Standard Packaging3000/Full Reel | ||
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Drivers, Receivers, Transceivers | |
| Manufacturer | Hangzhou Ruimeng Tech | |
| Packaging | TSSOP-56-6.1mm | |
| Voltage - Supply | 3.3V | |
| Type | Driver | |
| Data Rate | 1.05Gbps | |
| Number of Drivers | 4 | |
| Features | Low power standby / automatic shutdown on failure;Configurable output swing | |
| Level Standard | LVDS;TTL | |
| Number of Receivers | 0 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Drivers, Receivers, Transceivers | |
| Manufacturer | Hangzhou Ruimeng Tech | |
| Packaging | TSSOP-56-6.1mm | |
| Voltage - Supply | 3.3V | |
| Type | Driver |
| Type | Description | |
|---|---|---|
| Data Rate | 1.05Gbps | |
| Number of Drivers | 4 | |
| Features | Low power standby / automatic shutdown on failure;Configurable output swing | |
| Level Standard | LVDS;TTL | |
| Number of Receivers | 0 |
Introduction
The MS90C385B converts 28-bit TTL data into 4-channel LVDS signals. The clock channel is phase-locked and output in parallel with the data channels. At a clock frequency of 150MHz, 24-bit RGB data, 3-bit LCD timing data, and 1-bit control data are transmitted at 1050Mbps per LVDS data channel. At an input clock frequency of 150MHz, the data transfer rate is 525Mbytes/sec. This device is an ideal solution for addressing EMI and cable length issues associated with high-bandwidth, high-speed TTL signal interfaces.
Features
- Frequency range: 20 - 150MHz clock signal
- Reduced bus minimizes wiring size and cost
- Core supply voltage: 3.3V
- I/O supply voltage: 1.8V / 3.3V compatible
- Low-power mode
- Supports VGA, SVGA, XGA, SXGA
- Supports spread spectrum clock generation
- Integrated input jitter filter
- 525 Megabytes/sec bandwidth
- Reduced LVDS swing for lower EMI (200mV or 345mV LVDS swing selectable)
- PLL requires no external components
- Compliant with TIA/EIA-644 LVDS standard
C231930 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |



