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MICROCHIP KSZ8851SNLI-TR

Manufacturer
MICROCHIP
MPN
KSZ8851SNLI-TR
LCSC Part #
C220781
Packaging
QFN-32(5x5)
Customer #
Key Attributes
Single-Port Ethernet Controller with SPI
Datasheetpdf iconMICROCHIP KSZ8851SNLI-TR
RoHS Compliance2 documents available
In-Stock: 1,473
1,473 In stock, ships now
Minimum: 1Multiple: 1Sales Unit: Piece
Add to BOM List
QtyUnit PriceTotal Amount
1+$ 2.9544$ 2.95
10+$ 2.5216$ 25.22
30+$ 2.2505$ 67.52
100+$ 1.9745$ 197.45
500+$ 1.8488$ 924.40
1,000+$ 1.7949$ 1794.90
Standard Packaging1000/Full Reel
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Interface/Controllers
ManufacturerMICROCHIP
PackagingQFN-32(5x5)
MAC InterfaceSPI
Voltage - Supply3.3V;1.8V;2.5V
FeaturesLow-power mode;Programmable LED indication;Wake-up function
Integrated PHYYes
Communication InterfaceSPI
Operating Temperature-40℃~+85℃
Memory Space18KB
Ethernet Speed Standards10BASE-T;100BASE-TX
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Features

AI Translation
  • Integrated MAC and PHY Ethernet Controller Fully Compliant with IEEE 802.3/802.3u Standards
  • SPI with Clock Speeds up to 40 MHz for High Throughput Applications
  • Supports 10BASE-T/100BASE-TX
  • Supports IEEE 802.3x Full-Duplex Flow Control and Half-Duplex Backpressure Collision Flow Control
  • Supports RXQ and TXQ FIFO DMA for Fast Data Read and Write Transfers
  • Supports IP Header (IPv4)/TCP/UDP/ICMP Checksum Generation and Checking
  • Supports IPv6 TCP/UDP/ICMP Checksum Generation and Checking
  • Automatic 32-bit CRC Generation and Checking
  • Supports Simple Command and Data Phases in SPI Cycle for RXQ/TXQ FIFO and Registers Read/Write
  • Supports Multiple Data Frames for TXQ FIFO and RXQ FIFO without Additional Command Phase
  • Supports Flexible Byte (8-bit), Word (16-bit) and Double Word (32-bit) Read/Write Access to Internal Registers
  • Larger Internal Memory with 12K Bytes for RX FIFO and 6K Bytes for TX FIFO. Programmable Low, High, and Overrun Watermark for Flow Control in RX FIFO
  • Efficient Architecture Design with Configurable Host Interrupt Schemes to Minimize Host CPU Overhead and Utilization
  • Powerful and Flexible Address Filtering Scheme
  • Optional to Use External Serial EEPROM Configuration for MAC Address
  • Single 25 MHz Reference Clock for Both PHY and MAC
  • Single 3.3V Power Supply with Options for 1.8V, 2.5V, and 3.3V VDD I/O
  • Built-In Integrated 3.3V or 2.5V to 1.8V Low Noise Regulator (LDO) for Core and Analog Blocks
  • Enhanced Power Management Feature with Energy Detect Mode and Soft Power-Down Mode to Ensure Low-Power Dissipation During Device Idle Periods
  • Comprehensive LED Indicator Support for Link, Activity and 10/100 Speed (2 LEDs)
  • Low-Power CMOS Design
  • Commercial Temperature Range: 0℃ to +70℃
  • Industrial Temperature Range: -40℃ to +85℃
  • Available in 32-pin (5 mm x 5 mm) QFN Package
  • Supports Adding Two-Bytes Before Frame Header in Order for IP Frame Content with Double Word Boundary
  • LinkMD Cable Diagnostic Capabilities to Determine Cable Length, Diagnose Faulty Cables, and Determine Distance to Fault
  • Wake-on-LAN Functionality - Incorporates Magic Packet, Wake-Up Frame, Network Link State, and Detection of Energy Signal Technology
  • HP Auto MDI-X Crossover with Disable/Enable Option
  • Ability to Transmit and Receive Frames up to 2000 Bytes
  • 10BASE-T and 100BASE-TX Physical Layer Support
  • Auto-Negotiation: 10/100 Mbps Full- and Half-Duplex
  • Adaptive Equalizer
  • Baseline Wander Correction

Applications

AI Translation
  • Video/Audio Distribution Systems
  • Voice over IP (VoIP) and Analog Telephone Adapters (ATA)
  • Building Automation
  • Industrial Control Sensor Devices (Temperature, Pressure, Levels, and Valves)
  • Security, Motion Control, and Surveillance Cameras