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Nexperia S25FS512SAGMFI010 product image
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Nexperia S25FS512SAGMFI010RoHS

Manufacturer
Nexperia
MPN
S25FS512SAGMFI010
LCSC Part #
C21715631
Packaging
-
Customer #
Key Attributes
512Mbit 1.7V~2V 133MHz SPI Memory RoHS
Datasheetpdf iconNexperia S25FS512SAGMFI010
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1+$ 12.5113$ 12.51
210+$ 4.9922$ 1048.36
504+$ 4.8256$ 2432.10
1,008+$ 4.7438$ 4781.75
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory
ManufacturerNexperia
Packaging-
Operating Temperature-40℃~+85℃
FeaturesWrite enable latch;Power-on reset;Hardware write protection;Software write protection;Absolute write protection;ECC error correction
Memory Size512Mbit
Voltage - Supply1.7V~2V
Program / Erase Cycles100,000 cycles
Clock Frequency133MHz
Data Retention - TDR (Year)20 Years
Block Erase Time(tBE)-
Write Cycle Time(tWC)-
Page Programming Time (Tpp)-
InterfaceSPI
Standby Supply Current70uA
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Introduction

AI Translation

The S25FS512S device is a flash nonvolatile memory product. It uses MirrorBit technology, which stores two data bits in each memory array transistor, and Eclipse architecture, which dramatically improves program and erase performance. It is fabricated with 65 nm process lithography. The S25FS512S connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two-bit (Dual I/O or DIO) and four-bit wide Quad I/O (QIO) or Quad Peripheral Interface (QPI) serial commands. This multiple-width interface is called SPI Multi-I/O or MIO. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock. The FS-S Eclipse architecture features a Page Programming Buffer that allows up to 512 bytes to be programmed in one operation, resulting in faster effect.

Features

AI Translation
  • Serial Peripheral Interface (SPI) with Multi-I/O
  • SPI Clock polarity and phase modes 0 and 3
  • Double Data Rate (DDR) option
  • Extended Addressing – 24 or 32-bit address options
  • Serial Command subset and footprint compatible with S25FL-A, S25FL-K, S25FL-P, and S25FL-S SPI families
  • Multi I/O Command subset and footprint compatible with S25FL-P, and S25FL-S SPI families
  • Commands: Normal, Fast, Dual I/O, Quad I/O, DDR Quad I/O
  • Modes: Burst Wrap, Continuous (XIP), QPI
  • Serial Flash Discoverable Parameters (SFDP) and Common Flash Interface (CFI), for configuration information
  • 256 or 512 Bytes Page Programming buffer
  • Program suspend and resume
  • Automatic Error Checking and Correction (ECC) – internal hardware ECC with single bit error correction
  • Cycling Endurance: 100,000 Program-Erase Cycles, minimum
  • Data Retention: 20 Year Data Retention, minimum
  • Security Features: One Time Program (OTP) array of 1024 bytes
  • Block Protection: Status Register bits to control protection against program or erase of a contiguous range of sectors; Hardware and software control options
  • Advanced Sector Protection (ASP): Individual sector protection controlled by boot code or password; Option for password control of read access
  • Technology: Cypress 65-nm MirrorBit Technology with Eclipse Architecture
  • Supply Voltage: 1.7 V to 2.0 V
  • Temperature Range / Grade: Industrial -40℃ to +85℃; Industrial Plus -40℃ to +105℃; Automotive, AEC-Q100 Grade 3 -40℃ to +85℃; Automotive, AEC-Q100 Grade 2 -40℃ to +105℃; Automotive, AEC-Q100 Grade 1 -40℃ to +125℃
  • Packages (all Pb-free): 16-lead SOIC 300 mil (SO3016); WSON 6x8 mm (WNH008); BGA-24 6x8 mm • 5x5 ball (FAB024) footprint; Known Good Die and Known Tested Die