micron MT48LC8M8A2P-75 IT:G TR

The Micron 64Mb SDRAM is a high-speed CMOS dynamic random access memory containing 67,108,864 bits. It is internally configured as a four-bank DRAM with a synchronous interface (all signals are registered on the rising edge of the clock signal CLK). Each 16,777,216-bit bank in the x4 organization is arranged as 4,096 rows × 1,024 columns × 4 bits. Each 16,777,216-bit bank in the x8 organization is arranged as 4,096 rows × 512 columns × 8 bits. Each 16,777,216-bit bank in the x16 organization is arranged as 4,096 rows × 256 columns × 16 bits. Read and write accesses to the SDRAM are burst-oriented; access begins at a selected location and continues for a programmed number of locations in a programmed sequence. Access begins with the registration of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank; A0–A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides a programmable read or write burst length of 1, 2, 4, or 8 locations, or full page, with a burst terminate option. Auto precharge can be enabled to provide a self-timed row precharge initiated at the end of the burst sequence. The 64Mb SDRAM uses an internal pipeline architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of the prefetch architecture, but also allows the column address to be changed every clock cycle for high-speed, fully random access. Precharging one bank while accessing one of the other three banks hides the precharge cycle and provides seamless, high-speed, random access operation. The 64Mb SDRAM is designed for 3.3V memory systems. Auto refresh mode as well as a power-saving, power-down mode are provided. All inputs and outputs are LVTTL-compatible. The SDRAM offers significant improvements in DRAM operating performance, including the ability to synchronously burst data at high data rates with automatic column address generation, the ability to interleave between internal banks to hide precharge time, and the ability to randomly change the column address every clock cycle during burst access.

• Compliant with PC66, PC100, and PC133 standards
• Fully synchronous; all signals registered on the rising edge of the system clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal banks for hidden row access/precharge
• Programmable burst length: 1, 2, 4, 8, or full page
• Auto precharge, including concurrent auto precharge and auto refresh modes
• Self-refresh mode: standard and low-power modes
• 64ms, 4096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V supply