RENESAS R5F564MJDGFP#V1

120MHz 32-bit RX microcontroller with on-chip FPU, 240 DMIPS, up to 4MB flash, 512KB SRAM, multiple communication interfaces including IEEE 1588-compliant Ethernet MAC, full-speed USB 2.0 with battery charging, SD host interface (optional), quad SPI and CAN, 12-bit ADC, RTC, encryption (optional), audio serial interface, CMOS camera interface

• 32-bit RXv2 CPU core：
  • Max. operating frequency: 120 MHz，Capable of 240 DMIPS in operation at 120 MHz
  • Single precision 32-bit IEEE - 754 floating point
  • Two types of multiply - and - accumulation unit (between memories and between registers)
  • 32 - bit multiplier (fastest instruction execution takes one CPU clock cycle)
  • Divider (fastest instruction execution takes two CPU clock cycles)
  • Fast interrupt
  • CISC Harvard architecture with 5 - stage pipeline
  • Variable - length instructions: Ultra - compact code
  • Supports the memory protection unit (MPU)
  • JTAG and FINE (one - line) debugging interfaces
• Low - power design and architecture：
  • Single voltage supply: 2.7 to 3.6 V
  • Low power consumption: A product that supports all peripheral functions draws only 0.3mA/MHz (Typ.)
  • RTC is capable of operation from a dedicated power supply
  • Four low - power modes
• On - chip code flash memory, no wait states：
  • Up to 4 Mbyte
  • 120 - MHz operation, 8.3 - ns read cycle (no wait states)
  • User code is programmable by on - board or off - board programming
  • Background programming/erasing (BGO:Background operation)
• On - chip data flash memory：
  • 64 Kbytes, reprogrammable up to 100,000 times
  • Background programming/erasing (BGO:Background operation)
• On - chip SRAM：
  • 512 Kbytes of SRAM (no wait states)
  • 32 Kbytes of RAM with ECC (one wait state, single - error correction and double error detection)
  • 8 Kbytes of standby RAM (backup on deep software standby)
• Data transfer：
  • DMAC: 8 channels
  • DTC
  • EXDMAC: 2 channels
  • DMAC for the Ethernet controller: 3 channels for 176 - and 177 - pin products; 2 channels for 100 -, 144 -, and 145 - pin products
• Reset and supply management：
  • Power - on reset (POR)
  • Low voltage detection (LVD) with voltage settings
• Clock functions：
  • External crystal resonator or internal PLL for operation at 8 to 24 MHz
  • Internal 240 - kHz LOCO and HOCO selectable from 16, 18, and 20 MHz
  • 120 - kHz clock for the IWDTa
• Real - time clock：
  • Adjustment functions (30 seconds, leap year, and error)
  • Real - time clock counting and binary counting modes are selectable
  • Time capture function (for capturing times in response to event - signal input)
• Independent watchdog timer：
  • 120 - kHz (1/2 LOCO frequency) clock operation
• Useful functions for IEC60730 compliance：
  • Oscillation - stoppage detection, frequency measurement, CRC, IWDTa, self - diagnostic function for the A/D converter, etc.
  • Register write protection function can protect values in important registers against overwriting
• Various communications interfaces：
  • IEEE 1588 - compliant Ethernet MAC (for 176 - and 177 - pin products: 2 modules)
  • PHY layer for host/function or OTG controller (1) with full - speed USB 2.0 with battery charging transfer (only for 176 - and 177 - pin products)
  • PHY layer (1) for host/function or OTG controller (1) with full - speed USB 2.0 transfer
  • CAN (compliant with ISO11898 - 1), incorporating 32 mailboxes (up to 3 modules)
  • SCIg and SCIh with multiple functionalities (up to 9). Choose from among asynchronous mode, clock - synchronous mode, smart - card interface mode, simplified SPI, simplified I2C, and extended serial mode.
  • SCIFA with 16 - byte transmission and reception FIFOs (up to 4 interfaces)
  • I²C bus interface for transfer at up to 1 Mbps (up to 2 interfaces)
  • Four - wire QSPI (1 interface) in addition to RSPIa (1 interface)
  • Parallel data capture unit (PDC) for the CMOS camera interface (not in 100 - pin products)
  • SD host interface (optional: 1 interface) with a 1 - or 4 - bit SD bus for use with SD memory or SDIO
• External address space：
  • Buses for full - speed data transfer (max. operating frequency of 60 MHz)
  • 8 CS areas
  • 8 -, 16 -, or 32 - bit bus space is selectable per area
  • Independent SDRAM area (128 Mbytes)
• Up to 29 extended - function timers：
  • 16 - bit TPUa, MTU3a, and GPTA: input capture, output compare, PWM waveform output
  • 8 - bit TMRa (4 channels), 16 - bit CMT (4 channels), 32 - bit CMTW (2 channels)
• 12 - bit A/D converter：
  • Two 12 - bit units (8 channels for unit 0; 21 channels for unit 1)
  • Self diagnosis
  • Detection of analog input disconnection
• 12 - bit D/A converter: 2 channels
• Temperature sensor for measuring temperature within the chip
• Encryption (optional)：
  • AES (key lengths: 128, 192, and 256 bits)
  • DES (key lengths: 56 bits (DES); 3×56 bits (T - DES))
  • SHA (SHA - 1 (128), SHA - 2 (224 or 256), HMAC (160, 224, or 256))
  • 5 - V tolerance, open drain, input pull - up, switchable driving ability
• Operating temp. range：
  • D - version: - 40℃ to + 85℃
  • G - version: - 40℃ to + 105℃