FTDI UMFT601X

The UMFT60xx is an evaluation/development module with either FMC(LPC)/HSMC connectors for interfacing FTDI’s FT60x USB 3.0 Superspeed IC with external hardware. The UMFT60xx allows for bridging a FIFO bus to a USB3.0 host and evaluating the functionality of the FT60x. As a daughter card, the UMFT60xx must work with a FIFO master board which has either a FMC or HSMC connector. There are 4 models which provide different FIFO bus interfaces and data bit widths. The modules are designed such that they can plug into most FPGA development platforms supplied by vendors such as Xilinx or Altera. The UMFT60xx supports 2 parallel slave FIFO bus protocols (Multi-Channel FIFO / 245 Synchronous FIFO) with a data “burst” rate of up to 400MB/s.

• Supports USB 3.0 Super Speed (5Gbps)/USB 2.0 High Speed (480Mbps)/USB 2.0 Full Speed (12Mbps) transfer
• 4 IN channels and 4 OUT channels on FIFO bus connectivity
• Supports multi voltage I/O: 1.8V, 2.5V and 3.3V
• High speed connector for FIFO bus: FMC(Field Programmable Mezzanine Card) or HSMC (High Speed Mezzanine Card)
• FMC connector is compatible with most Xilinx FPGA reference design boards
• HSMC is compatible with most Altera FPGA reference design boards
• Multi powered options: external DC powered, BUS powered, FMC/HSMC powered
• Hardware Reset and Remote Wake Up
• Micro-USB3.0 receptacle
• Provides Multi-channel FIFO mode and 245 Synchronous FIFO mode Protocols, configured by GPIOs
• Configurable FIFO clock: 66.67MHz and 100MHz (100MHz only for 2.5V or 3.3V VCCIO), default clock is 100MHz
• High speed FIFO bus interface: FMC (Low Pin Count) and HSMC optional
• Jumpers selection allowing powered options: VBUS-powered, External DC-powered, FIFO master board-powered
• Multi voltage VCCIO option: 1.8V, 2.5V, 3.3V
• Configurable GPIOs
• Hardware reset and remote wake up support
• Available with 16bit and 32bit wide FIFO bus