Nexperia 74AHCT74D-Q100,118

Dual D-type flip-flop with set and reset; positive-edge triggered. It is a high-speed Si-gate CMOS device, pin-compatible with low-power Schottky TTL (LSTTL), and compliant with JEDEC Standard No. 7-A. The device consists of two positive-edge triggered D-type flip-flops, each with individual data input (D), clock input (CP), set input (SD), and reset input (RD). It also features complementary outputs (Q and Q̄). Set and reset are asynchronous active-LOW inputs that operate independently of the clock input. When the clock pulse transitions from LOW to HIGH, the information present at the data input is transferred to the Q output. To ensure predictable operation, the data input must remain stable for one setup time prior to the LOW-to-HIGH clock transition. The Schmitt-trigger action on the clock input allows the circuit to tolerate slower clock rise and fall times. This product is qualified to Automotive Electronics Council (AEC) standard Q100 (Grade 1) for automotive applications.