Insignis Technology Corporation NDL56PFJ-8KIT TR

The 512Mb DDR3/3L SDRAM uses a double data rate architecture to achieve high-speed double data rate transfers of up to 1866Mb/s/pin in general-purpose applications. It is internally configured as eight banks of DRAM. The 512Mb device is organized as 4Mbit x 16 I/O x 8 banks.

The device is designed to comply with all DDR3/3L DRAM key features, including full backward compatibility from DDR3L to DDR3. All control and address inputs are synchronized to a pair of externally supplied differential clocks, with inputs latched at the differential clock crossing point (rising CK and falling CK#). All I/Os are source-synchronous, synchronized with differential DQS pairs.

DDR3L devices operate from a single +1.35V -0.067V/+0.1V or +1.5V ±0.075V supply, while DDR3 devices operate from a single 1.5V ±0.075V supply. All devices are available in BGA packages.

DDR3/3L SDRAM is a high-speed DRAM internally configured as eight banks. It employs an 8n-prefetch architecture for high-speed operation. Combined with the interface, the 8n-prefetch architecture enables two data words to be transferred per clock cycle at the I/O pins. A single read or write operation consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core, and two corresponding n-bit wide, half-clock-cycle data transfers at the I/O pins.

Read and write accesses to the DDR3/3L SDRAM are burst-oriented, starting from a selected location and continuing for a burst length of eight or a "truncated" burst length of four in a programmed sequence. Operations begin with the registration of an ACTIVE command, followed by a READ or WRITE command. Address bits registered coincident with the ACTIVE command are used to select the bank and row to be activated (BA0–BA2 select the bank; A0–A11 select the row). Address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst operation, to determine whether an Auto Precharge command is to be issued (via A10), and to select BC4 or BL8 mode "on the fly" (via A12) when enabled by the Mode Register.

Prior to normal operation, the DDR3/3L SDRAM must be powered up and initialized in a predefined manner. The following sections provide detailed information on device reset and initialization, register definitions, command descriptions, and device operation.

• JEDEC compliant
• AEC-Q100 compliant (optional)
• Power supply: VDD and VDDQ = +1.35V (1.283V ~ 1.45V) (DDR3L only)
• Backward compatible with VDD and VDDQ = +1.5V ±0.075V (DDR3 or DDR3L)
• Operating temperature range:
  • Extended Test (ET): TC = 0 ~ 95°C
  • Industrial (IT): TC = -40 ~ 95°C
  • Automotive (AT): TC = -40 ~ 105°C
• JEDEC clock jitter specification compliant
• Fully synchronous operation
• Fast clock rates: 667/800/933MHz
• Differential clock, CK and CK#
• Bidirectional differential data strobe — DQS and DQS#
• 8 internal banks with concurrent operation
• 8n-bit prefetch architecture
• Pipelined internal architecture
• Precharge and active power-down
• Programmable mode and extended mode registers
• Additive Latency (AL): 0, CL-1, CL-2
• Programmable burst length: 4, 8
• Burst type: sequential/interleaved
• Output driver impedance control
• Average refresh period:
  • 8192 cycles/64ms (7.8us at -40°C ≤ Tc ≤ +85°C)
  • 8192 cycles/32ms (3.9us at +85°C ≤ Tc ≤ +95°C)
  • 8192 cycles/16ms (1.95us at +95°C ≤ Tc ≤ +105°C)
• Write leveling
• ZQ calibration
• Dynamic ODT (Rtt_Nom and Rtt_WR)
• RoHS compliant
• Auto refresh and self-refresh
• 96-ball 8×13×1.0mm FBGA package
• Lead-free and halogen-free