Lattice LAXP2-5E-5QN208E

LA - LatticeXP2 devices combine LUT-based FPGA architecture with non-volatile flash cells in an architecture called flexiFLASH. The flexiFLASH architecture offers instant-on, unlimited reconfigurability, on-chip storage (with FlashBAK embedded block memory and serial TAG memory), and design security. These devices also support live update technologies, including TransFR, 128-bit AES encryption, and dual-boot capability. The LA - LatticeXP2 FPGA architecture was optimized from the ground up for new technologies, balancing high performance with low cost. LA - LatticeXP2 devices include LUT-based logic, distributed and embedded memory, PLLs, pre-engineered source-synchronous I/O support, and enhanced sysDSP blocks. Lattice Diamond design software enables efficient implementation of large, complex designs using LA - LatticeXP2 family FPGA devices. Popular logic synthesis tools provide synthesis library support for LA - LatticeXP2. Diamond software uses the output from synthesis tools along with constraints from floorplanning tools to perform place-and-route of designs in LA - LatticeXP2 devices. The Diamond design tool extracts timing information from routing and back-annotates it into the design for timing verification. Lattice offers numerous pre-designed LatticeCORE™ IP modules for the LA - LatticeXP2 family. By using these IP cores as standardized building blocks, designers can focus on the unique aspects of their designs, improving productivity. Each LA - LatticeXP2 device contains an array of logic blocks surrounded by a ring of programmable I/O cells (PICs). Rows of sysMEM™ embedded block RAM (EBR) and a row of sysDSP™ digital signal processing blocks are interspersed between the logic block rows. Non-volatile memory blocks are located on the left and right sides of the programmable function unit (PFU) array. In configuration mode, the non-volatile memory is programmed via the IEEE 1149.1 TAP port or the sysCONFIG™ peripheral port. At power-up, configuration data is transferred from the non-volatile memory blocks to the configuration SRAM. This approach eliminates the need for costly external configuration memory and protects designs from unauthorized readback. Data transfer from non-volatile memory to configuration SRAM via a wide bus completes in microseconds, providing an "instant-on" capability that simplifies interfacing in many applications. LA - LatticeXP2 devices can also transfer data from sysMEM EBR blocks to non-volatile memory blocks upon user request. There are two types of logic blocks: PFU and PFU without RAM (PFF). PFUs contain building blocks for logic, arithmetic, RAM, and ROM functions. PFF blocks contain building blocks for logic, arithmetic, and ROM functions. Both PFU and PFF blocks are optimized for flexibility, enabling fast and efficient implementation of complex designs. Logic blocks are arranged in a two-dimensional array. Each row uses only one type of block. LA - LatticeXP2 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBR are large, dedicated 18 kbit memory blocks. Each sysMEM block can be configured as RAM or ROM in various depths and widths. Additionally, LA - LatticeXP2 devices contain up to two rows of DSP blocks. Each DSP block contains multipliers and adder/accumulators, which are the building blocks for implementing complex signal processing functions. Each PIC block contains two PIOs (a PIO pair) with their respective sysIO buffers. The sysIO buffers of LA - LatticeXP2 devices are divided into eight banks, allowing support for multiple I/O standards. PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. PIC logic also includes pre-engineered support to facilitate implementation of high-speed source-synchronous standards, such as the 7:1 LVDS interface used in many display applications, as well as memory interfaces including DDR and DDR2. Other available blocks include PLLs and configuration functions. The LA - LatticeXP2 architecture provides up to four general-purpose PLLs (G)

• flexiFLASH Architecture:
  • Instant-on
  • Unlimited reconfigurability
  • Single chip
  • FlashBAK technology
  • Serial TAG memory
  • Design security
  • AEC-Q100 tested and qualified
• Real-time update technology:
  • TransFR technology
  • Secure update with 128-bit AES encryption
  • External SPI dual-boot support
• sysDSP blocks:
  • Three to five blocks for high-performance multiply and accumulate
  • 12 to 2 18×18 multipliers
  • Each block supports one 36×36, four 18×18, or eight 9×9 multipliers
• Embedded and distributed memory:
  • Up to 276 kbits sysMEM EBR
  • Up to 35 kbits distributed RAM
• sysCLOCK PLL:
  • Up to four analog PLLs per device
  • Clock multiplication, division, and phase shifting
• Flexible I/O buffers:
  • sysIO buffers support: LVCMOS 33/25/18/15/12; LVTTL, SSTL 33/25/18 Class I, II, HSTL15 Class I; HSTL18 Class I, II, PCI, LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS
• Pre-engineered source-synchronous interfaces:
  • Up to 200 MHz DDR/DDR2 interface
  • 7:1 LVDS interface for display applications
  • XGMII
• Density and package options:
  • 5k to 17k LUT4s, 86 to 358 I/Os
  • csBGA, ftBGA, TQFP, and PQFP packages
  • Density migration support
• Flexible device configuration:
  • SPI (master/slave) boot flash interface
  • Dual-boot image support
  • Embedded soft error detection (SED) macro
• System-level support:
  • IEEE 1149.1 and IEEE 1532 compliant
  • On-chip oscillator for initialization and general use
  • 1.2 V core supply voltage