MAXIM MAX105ECS+
| Manufacturer | |
| MPN | MAX105ECS+ |
| LCSC Part # | C1543158 |
| Packaging | HTQFP-80(12x12) |
| Customer # | |
| Key Attributes | LVDS 5V HTQFP-80(12x12) Analog to Digital Converters (ADC) RoHS |
| Datasheet | |
| RoHS Compliance | 1 documents available |
Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC) | |
| Manufacturer | MAXIM | |
| Packaging | HTQFP-80(12x12) | |
| Operating Temperature | -40℃~+85℃ | |
| Interface | LVDS | |
| Quiescent Current (Iq) | - | |
| Voltage - Supply | 5V | |
| Number of Channels | 2 | |
| Integral non - linearity | 0.25LSB | |
| Voltage Reference | Built-in | |
| Clock/Oscillator | External | |
| Clock Frequency | - | |
| Features | Input buffer;Multiplexers | |
| Resolution(Bits) | 800MHz;6 | |
| S/N Ratio | 37dB | |
| DNL (LSB) | 0.25LSB | |
| ADC architecture | Flash | |
| Programmable Gain | Not supported |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC) | |
| Manufacturer | MAXIM | |
| Packaging | HTQFP-80(12x12) | |
| Operating Temperature | -40℃~+85℃ | |
| Interface | LVDS | |
| Quiescent Current (Iq) | - | |
| Voltage - Supply | 5V | |
| Number of Channels | 2 | |
| Integral non - linearity | 0.25LSB |
| Type | Description | |
|---|---|---|
| Voltage Reference | Built-in | |
| Clock/Oscillator | External | |
| Clock Frequency | - | |
| Features | Input buffer;Multiplexers | |
| Resolution(Bits) | 800MHz;6 | |
| S/N Ratio | 37dB | |
| DNL (LSB) | 0.25LSB | |
| ADC architecture | Flash | |
| Programmable Gain | Not supported |
Report an ErrorShow similar products (0) >
Features
AI Translation
- Dual matched 6-bit, 800Msps ADCs
- Excellent dynamic performance: SINAD of 36.4dB at fIN ≈ 200MHz and fCLK ≈ 800MHz
- Typical INL and DNL: ±0.25LSB
- Channel-to-channel phase matching: ±0.2°
- Channel-to-channel gain matching: ±0.04dB
- 6:12 demultiplexer reduces data rate to 400MHz
- Low error rate: one metastability error per 10^16 clock cycles at 800Msps
- LVDS digital outputs in two's complement format
Applications
AI Translation
- VSAT receivers
- WLANs
- Test instruments
- Communication systems
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| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 55.2148 | $ 55.21 |
| 238+ | $ 21.3685 | $ 5085.70 |
| 476+ | $ 20.6166 | $ 9813.50 |
| 952+ | $ 20.2461 | $ 19274.29 |
Standard Packaging119/Full Tray | ||
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Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC) | |
| Manufacturer | MAXIM | |
| Packaging | HTQFP-80(12x12) | |
| Operating Temperature | -40℃~+85℃ | |
| Interface | LVDS | |
| Quiescent Current (Iq) | - | |
| Voltage - Supply | 5V | |
| Number of Channels | 2 | |
| Integral non - linearity | 0.25LSB | |
| Voltage Reference | Built-in | |
| Clock/Oscillator | External | |
| Clock Frequency | - | |
| Features | Input buffer;Multiplexers | |
| Resolution(Bits) | 800MHz;6 | |
| S/N Ratio | 37dB | |
| DNL (LSB) | 0.25LSB | |
| ADC architecture | Flash | |
| Programmable Gain | Not supported |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC) | |
| Manufacturer | MAXIM | |
| Packaging | HTQFP-80(12x12) | |
| Operating Temperature | -40℃~+85℃ | |
| Interface | LVDS | |
| Quiescent Current (Iq) | - | |
| Voltage - Supply | 5V | |
| Number of Channels | 2 | |
| Integral non - linearity | 0.25LSB |
| Type | Description | |
|---|---|---|
| Voltage Reference | Built-in | |
| Clock/Oscillator | External | |
| Clock Frequency | - | |
| Features | Input buffer;Multiplexers | |
| Resolution(Bits) | 800MHz;6 | |
| S/N Ratio | 37dB | |
| DNL (LSB) | 0.25LSB | |
| ADC architecture | Flash | |
| Programmable Gain | Not supported |
Report an ErrorShow similar products (0) >
Features
AI Translation
- Dual matched 6-bit, 800Msps ADCs
- Excellent dynamic performance: SINAD of 36.4dB at fIN ≈ 200MHz and fCLK ≈ 800MHz
- Typical INL and DNL: ±0.25LSB
- Channel-to-channel phase matching: ±0.2°
- Channel-to-channel gain matching: ±0.04dB
- 6:12 demultiplexer reduces data rate to 400MHz
- Low error rate: one metastability error per 10^16 clock cycles at 800Msps
- LVDS digital outputs in two's complement format
Applications
AI Translation
- VSAT receivers
- WLANs
- Test instruments
- Communication systems
C1543158 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |

