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Cirrus Logic CS8900A-CQZ product image
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Cirrus Logic CS8900A-CQZ

Manufacturer
MPN
CS8900A-CQZ
LCSC Part #
C1521566
Packaging
LQFP-100-EP(14x14)
Customer #
Key Attributes
LQFP-100-EP(14x14) Drivers, Receivers, Transceivers RoHS
Datasheetpdf iconCirrus Logic CS8900A-CQZ
RoHS Compliance1 documents available
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QtyUnit Price(Reference Only)Total Amount
1+$ 8.6757$ 8.68
200+$ 3.3581$ 671.62
500+$ 3.2391$ 1619.55
1,000+$ 3.1821$ 3182.10
Standard Packaging90/Full Tray
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Interface/Drivers, Receivers, Transceivers
ManufacturerCirrus Logic
PackagingLQFP-100-EP(14x14)
Voltage - Supply3V;5V
Operating Temperature0℃~+70℃
FeaturesPower-on reset;Programmable LED indication;Low-power mode;Error detection and recovery
Interface-

Introduction

AI Translation

The CS8900A is a low-cost Ethernet LAN controller optimized for industry-standard architecture buses and general-purpose microcontroller buses. Its highly integrated design eliminates the need for costly external components required by other Ethernet controllers. The controller incorporates on-chip RAM, 10BASE-T transmit and receive filters, and a direct ISA bus interface with 24 mA drivers. Beyond its high level of integration, it offers an extensive set of performance features and configuration options. The unique PacketPage architecture automatically adapts to changing network traffic patterns and available system resources, improving system efficiency. The device is housed in a 100-pin LQFP package, making it ideal for space-constrained, cost-sensitive Ethernet applications. Using this controller, system engineers can design a complete Ethernet circuit occupying less than 1.5 square inches of board area.

Features

AI Translation
  • Single-chip IEEE 802.3 Ethernet controller with direct ISA bus interface
  • Maximum current consumption: 55 mA
  • Supports 3V or 5V operation
  • Industrial temperature range
  • Comprehensive software driver suite
  • Efficient PacketPage architecture supporting I/O and memory space operation, and DMA slave mode
  • Full-duplex operation
  • On-chip RAM buffering for transmit and receive frames
  • 10BASE-T port with analog filter, automatic polarity detection and correction
  • AUI port supporting 10BASE2, 10BASE5, and 10BASE-F
  • Programmable transmit features: automatic retransmission on collision, auto-padding, and CRC generation
  • Programmable receive features: streaming technology to reduce CPU overhead, automatic switching between DMA and on-chip memory, early interrupt for frame preprocessing, automatic rejection of errored packets
  • EEPROM support for jumperless configuration
  • Boot PROM support for diskless systems
  • Boundary scan and loopback testing
  • LED drivers for link status and LAN activity indication
  • Standby and suspend sleep modes