RENESAS R5F10277GNA#45

True low-power platform (63 μA/MHz) for the general-purpose applications, with 1.8-V to 5.5-V operation, 2- to 16-Kbyte code flash memory, and 31 DMIPS at 24 MHz

• Ultra-low power consumption technology
  • VDD = single power supply voltage of 1.8 to 5.5 V which can operate at a low voltage
  • HALT mode
  • STOP mode
  • SNOOZE mode
• RL78 CPU core
  • CISC architecture with 3-stage pipeline
  • Minimum instruction execution time: Can be changed from high speed (0.04167 μs @ 24 MHz operation with high-speed on-chip oscillator) to ultra-low speed (Δ μs @ 1 MHz operation)
  • Address space: 1 MB
  • General-purpose registers: (8-bit register x 8) x 4 banks
  • On-chip RAM: 256 B to 2 KB
• Code flash memory
  • Code flash memory: 2 to 16 KB
  • Block size: 1 KB
  • Prohibition of block erase and rewriting (security function) On-chip debug function
  • Self-programming (with flash shield window function)
• Data flash memory
  • Data flash memory: 2 KB Back ground operation (BGO): Instructions are executed from the program memory while rewriting the data flash memory.
  • Number of rewrites: 1,000,000 times (TYP.)
  • Voltage of rewrites: VDD = 1.8 to 5.5 V
• High-speed on-chip oscillator
  • Select from 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz High accuracy: +/- 1.0% (VDD = 1.8 to 5.5 V, TA = -20 to +85 °C)
• Operating ambient temperature
  • TA = -40 to +85 °C (A: Consumer applications, D: Industrial applications)
  • TA = -40 to +105 °C (G: Industrial applications)
• Power management and reset function
  • On-chip power-on-reset (POR) circuit On-chip voltage detector (LVD) (Select interrupt and reset from 12 levels)
• DMA (Direct Memory Access) controller
  • 2 channels Number of clocks during transfer between 8/16-bit SFR and internal RAM: 2 clocks
• Multiplier and divider/multiply-accumulator
  • 16 bits x 16 bits = 32 bits (Unsigned or signed)
  • 32 bits x 32 bits = 32 bits (Unsigned)
  • 16 bits x 16 bits + 32 bits = 32 bits (Unsigned or signed)
• Serial interface
  • CSI : 1 to 3 channels
  • UART : 1 to 3 channels
  • Simplified I²C communication : 0 to 3 channels
  • I²C communication : 1 channel
• Timer
  • 16-bit timer : 4 to 8 channels
  • 12-bit interval timer : 1 channel
  • Watchdog timer : 1 channel (operable with the dedicated low-speed on-chip oscillator)
• A/D converter
  • 8/10-bit resolution A/D converter (VDD = 1.8 to 5.5 V)
  • 8 to 11 channels, internal reference voltage (1.45 V), and temperature sensor
• I/O port
  • I/O port: 18 to 26 (N-ch open drain I/O [withstand voltage of 6 V]: 2, N-ch open drain I/O [VDD withstand voltage]: 4 to 9) Can be set to N-ch open drain, TTL input buffer, and on-chip pull-up resistor Different potential interface: Can connect to a 1.8/2.5/3 V device
  • On-chip key interrupt function
  • On-chip clock output/buzzer output controller
• Others
  • On-chip BCD (binary-coded decimal) correction circuit