Infineon/CYPRESS CY8C4045PVS-S412

PSoC 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an ARM Cortex - M0+ CPU while being AEC - Q100 compliant. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4000S product family is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard communication and timing peripherals, a capacitive touch - sensing system (CapSense) with best - in - class performance, programmable general - purpose continuous - time and switched - capacitor analog blocks, and programmable connectivity. PSoC 4000S products will be upward compatible with members of the PSoC 4 platform for new applications and design needs.

• Automotive Electronics Council (AEC) AEC - Q100 Qualified
• 48 - MHz ARM Cortex - M0+ CPU
• Up to 32 KB of flash with Read Accelerator
• Up to 4 KB of SRAM
• Single - slope 10 - bit ADC function provided by Capacitance sensing block
• Two current DACs (IDACs) for general - purpose or capacitive sensing applications on any pin
• Two low - power comparators that operate in Deep Sleep low - power mode
• Programmable logic blocks allowing Boolean operations to be performed on port inputs and outputs
• Deep Sleep mode with operational analog and 2.5 μA digital system current
• Cypress CapSense Sigma - Delta (CSD) provides best - in - class signal - to - noise ratio (SNR) (>5;1) and water tolerance
• Cypress - supplied software component makes capacitive sensing design easy
• Automatic hardware tuning (SmartSense™)
• Two independent run - time reconfigurable Serial Communication Blocks (SCBs) with re - configurable I2C, SPI, or UART functionality
• LCD segment drive capability on GPIOs
• Five 16 - bit timer/counter/pulse - width modulator (TCPWM) blocks
• Center - aligned, Edge, and Pseudo - random modes
• Comparator - based triggering of Kill signals for motor drive and other high - reliability digital logic applications
• 24 - pin QFN and 28 - pin SSOP packages
• Any GPIO pin can be CapSense, analog, or digital
• Drive modes, strengths, and slew rates are programmable
• Integrated Development Environment (IDE) provides schematic design entry and build (with analog and digital automatic routing)
• Applications Programming Interface (API) component for all fixed - function and programmable peripherals
• After schematic entry, development can be done with ARM - based industry - standard development tools
• A - Grade: - 40 ℃ to + 85 ℃
• S - Grade: - 40 ℃ to + 105 ℃
• Allows disabling of debug features
• Robust flash protection
• Allows customer - proprietary functionality to be implemented in on - chip programmable blocks