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MICROCHIP PIC24FJ64GL306-I/MRRoHS

Manufacturer
MICROCHIP
MPN
PIC24FJ64GL306-I/MR
LCSC Part #
C1019303
Packaging
QFN-64(9x9)
Customer #
Key Attributes
PIC 16 Bit 32MHz 52 QFN-64(9x9) Microcontrollers RoHS
Datasheetpdf iconMICROCHIP PIC24FJ64GL306-I/MR
Alternative Parts4
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QtyUnit Price(Reference Only)Total Amount
1+$ 2.5514$ 2.55
200+$ 0.9879$ 197.58
500+$ 0.9539$ 476.95
1,000+$ 0.9369$ 936.90
Standard Packaging40/Full Tube
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/Microcontrollers
ManufacturerMICROCHIP
PackagingQFN-64(9x9)
ADC (Bit)10bit;12bit
Operating Temperature-40℃~+85℃
Voltage - Supply2V~3.6V
Program Memory TypeFLASH
EEPROM-
Program Storage Size64KB
CPU CorePIC
Core Size16 Bit
CPU Maximum Speed32MHz
Oscillator TypeExternal
Number of I/O52
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Features

AI Translation
  • Modified Harvard Architecture
  • 128 Kbytes Flash Memory
  • 8 Kbytes SRAM
  • Up to 16 MIPS Operation @32 MHz
  • 17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier
  • 32-Bit by 16-Bit Hardware Divider
  • 16-Bit x 16-Bit Working Register Array
  • C Compiler Optimized Instruction Set Architecture
  • Two Address Generation Units (AGUs) for Separate Read and Write Addressing of Data Memory
  • 32x8 with Up to 256 Pixels
  • LCD Charge Pump
  • Core-Independent LCD Animation
  • Operation in Sleep mode
  • Up to 17-Channel, Software-Selectable, 10/12-Bit Analog-to-Digital Converter:
    • 12-bit, 350K samples/second conversion rate (single Sample-and-Hold)
    • 10-bit, 400K samples/second conversion rate (single Sample-and-Hold)
    • Sleep mode operation
    • Low-voltage boost for input
    • Band gap reference input feature
    • Core-independent windowed threshold compare feature
    • Auto-scan feature
  • Three Analog Comparators with Input Multiplexing:
    • Programmable reference voltage for comparators
  • Sleep and Idle modes Selectively Shut Down Peripherals and/or Core for Substantial Power Reduction and Fast Wake-up
  • Doze mode Allows CPU to Run at a Lower Clock Speed than Peripherals
  • Alternate Clock modes Allow On-the-Fly Switching to a Lower Clock Speed for Selective Power Reduction
  • Retention Sleep with On-Chip Ultra Low-Power Retention Regulator
  • Fail-Safe Clock Monitor Operation:
    • Detects clock failure and switches to on-chip, low-power RC oscillator
  • Power-on Reset (POR), Brown-out Reset (BOR)
  • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
  • Programmable High/Low-Voltage Detect (HLVD)
  • Flexible Watchdog Timer (WDT) with RC Oscillator for Reliable Operation
  • Deadman Timer (DMT) for Monitoring Health of Software
  • Programmable 32-Bit Cyclic Redundancy Check (CRC) Generator
  • Flash OTP by ICSP Write Inhibit
  • CodeGuard Security
  • ECC Flash Memory (128 Kbytes) with Fault Injection:
    • Single Error Correction (SEC)
    • Double Error Detection (DED)
  • Customer OTP Memory
  • Unique Device Identifier (UDID)
  • Supply Voltage Range of 2.0V to 3.6V
  • Operating Ambient Temperature Range of -40°C to +125°C
  • On-Chip Voltage Regulators (1.8V) for Low-Power Operation
  • Flash Memory:
    • 10,000 erase/write cycle endurance, typical
    • Data retention: 20 years minimum
    • Self-programmable under software control
    • Flash OTP emulation
  • 8 MHz Fast RC Internal Oscillator:
    • Multiple clock divide options
    • Fast start-up
  • 96 MHz PLL Option
  • Programmable Reference Clock Output
  • In-Circuit Serial Programming (ICSP) and In-Circuit Emulation (ICE) via Two Pins
  • JTAG Boundary Scan Support
  • Independent, Low-Power 32 kHz Timer Oscillator
  • Six-Channel DMA Controller:
    • Minimizes CPU overhead and increases data throughput
  • Timer1: 16-Bit Timer/Counter with External Crystal Oscillator; Timer1 can Provide an A/D Trigger
  • Timer2,3,4,5: 16-Bit Timer/Counter can Create 32-Bit Timer; Timer3 and Timer5 can Provide an A/D Trigger
  • Five MCCP modules, Each with a Dedicated 16/32-Bit Timer:
    • One 6-output MCCP module
    • Four 2-output MCCP modules
  • Two Variable Width, Serial Peripheral Interface (SPI) Ports on All Devices; Three Operation modes:
    • 3-wire SPI (supports all four SPI modes)
    • Up to 32-byte deep FIFO buffer
    • I²S mode
    • Speed up to 25 MHz
  • Two I²C Master and Slave w/Address Masking, PMBus and IPMI Support
  • Four UART modules:
    • LIN/J2602 bus support (auto-wake-up, Auto-Baud Detect, Break character support)
    • RS-232 and RS-485 support
    • IrDA mode (hardware encoder/decoder functions)
  • Five External Interrupt Pins
  • Hardware Real-Time Clock and Calendar (RTCC)
  • Peripheral Pin Select (PPS) allows Independent I/O Mapping of Many Peripherals
  • Configurable Interrupt-on-Change on All I/O Pins:
    • Each pin is independently configurable for rising edge or falling edge change detection
  • Reference Clock Output with Programmable Divider
  • Four Configurable Logic Cell (CLC) Blocks:
    • Two inputs and one output, all mappable to peripherals or I/O pins
    • AND/OR/XOR logic and D/JK flip-flop functions
  • AEC-Q100 REVG (Grade 1: -40°C to +125°C) Compliant

Alternative Parts

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