ADI AD4007BRMZ-RL7

AD4003 is a low noise, low power, high speed, 18-bit, 2 MSPS precision successive approximation register (SAR) ADC. It integrates ease-of-use features that reduce signal chain power consumption and complexity while supporting higher channel density. The combination of a high-Z mode and a long acquisition phase extends the range of low power precision amplifiers that can directly drive this ADC without requiring dedicated high power, high speed ADC drivers, while still achieving excellent performance. The input span compression feature allows the ADC driver amplifier and ADC to share a common supply rail without the need for a negative supply, while preserving the full ADC code range. Low SPI clock rate requirements reduce digital I/O power consumption, broaden processor options, and simplify the process of sending data across digital isolators.

The AD4003 operates from a 1.8 V supply with a ±VREF fully differential input range, where VREF ranges from 2.4 V to 5.1 V. In turbo mode, the AD4003 operating at a 75 MHz SCK rate (minimum) at 2 MSPS consumes only 16 mW, achieving ±1.0 LSB INL (±3.8 ppm maximum), guaranteed 18-bit no missing codes, and 100.5 dB SNR (typical). The reference voltage is supplied externally and can be independent of the supply voltage.

The SPI-compatible versatile serial interface provides seven different modes, including the ability to daisy-chain multiple ADCs onto a single 3-wire bus using the SDI input, with optional busy indication. Using a separate VIO supply, the AD4003 is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic.

The AD4003 is available in a 10-lead MSOP or 10-lead LFCSP package and is specified over the −40°C to +125°C temperature range. The device is pin compatible with the 16-bit, 2 MSPS AD4000.

• Throughput rate: 2 MSPS (max)
• INL: ±1.0 LSB (±3.8 ppm, max)
• Low power: 9.5 mW (2 MSPS, VDD only), 80 μW (10 kSPS), 16 mW (2 MSPS) (total)
• SNR: 100.5 dB (typical, 1 kHz), 99 dB (typical, 100 kHz)
• THD: -123 dB (typical, 1 kHz), -100 dB (typical, 100 kHz)
• Ease-of-use features reduce system power and complexity
• Input overvoltage clamp circuit reduces nonlinear input charge kickback
• High-Z mode
• Long acquisition phase
• Input span compression
• Fast conversion time
• Support for very low SPI clock rates
• SPI programmable modes, read/write capability, status word
• Differential analog input range: ±VREF, 0 V to VREF (VREF from 2.4 V to 5.1 V)
• Single-supply operation: 1.8 V, logic interface voltage: 1.71 V to 5.5 V
• SAR architecture: no latency/pipeline delay
• Guaranteed operation: -40°C to 125°C
• Serial interface SPI/QSPI/MICROWIRE/DSP compatible
• Daisy-chainable multiple ADCs with busy indicator
• 10-lead package: 3 mm×3 mm LFCSP and 3 mm×4.90 mm MSOP

• Automatic test equipment
• Machine automation
• Medical equipment
• Battery-powered devices
• Precision data acquisition systems