Infineon CY9AF342LAPMC-GNE2
| Manufacturer | |
| MPN | CY9AF342LAPMC-GNE2 |
| LCSC Part # | C6206512 |
| Packaging | LQFP-64(12x12) |
| Customer # | |
| Key Attributes | ARM Cortex-M3 32 Bit 40MHz 51 LQFP-64(12x12) Microcontrollers RoHS |
| Datasheet | |
| RoHS Compliance | 1 documents available |
| Alternative Parts | 10 |
Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | Infineon | |
| Packaging | LQFP-64(12x12) | |
| ADC (Bit) | 12bit | |
| Operating Temperature | -40℃~+85℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 1.65V~3.6V | |
| EEPROM | - | |
| Program Storage Size | 160KB | |
| CPU Core | ARM Cortex-M3 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 40MHz | |
| Oscillator Type | Built-in+External | |
| Number of I/O | 51 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | Infineon | |
| Packaging | LQFP-64(12x12) | |
| ADC (Bit) | 12bit | |
| Operating Temperature | -40℃~+85℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 1.65V~3.6V |
| Type | Description | |
|---|---|---|
| EEPROM | - | |
| Program Storage Size | 160KB | |
| CPU Core | ARM Cortex-M3 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 40MHz | |
| Oscillator Type | Built-in+External | |
| Number of I/O | 51 |
Report an ErrorShow similar products (0) >
Introduction
AI Translation
CY9A340NB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, and Communication Interfaces (USB, UART, CSIO, I²C).
Features
AI Translation
- 32-bit ARM Cortex-M3 Core
- Processor version: r2p1
- Up to 40 MHz Frequency Operation
- Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels
- 24-bit System timer (Sys Tick): System timer for OS task management
- On-chip Memories
- [Flash memory]
- Dual Operation Flash memory has the upper bank and the lower bank. So, this series could implement erase, write and read operations for each bank simultaneously.
- Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank)
- Work area: 32 Kbytes (lower bank)
- Read cycle: 0 wait-cycle Security function for code protection
- [SRAM]
- This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.
- SRAM0: Up to 16 Kbytes SRAM1: Up to 16 Kbytes
- [Flash memory]
- External Bus Interface
- Supports SRAM, NOR Flash memory device
- Up to 8 chip selects
- 8-/16-bit Data width
- Up to 25-bit Address bit
- Maximum area size: Up to 256 Mbytes
- Supports Address/Data multiplex
- Supports external RDY function
- USB Interface
- [USB device]
- USB2.0 Full-Speed supported Max 6 EndPoint supported
- EndPoint 0 is control transfer
- EndPoint 1, 2 can select Bulk-transfer, Interrupt-transfer or Isochronous-transfer
- EndPoint 3 to 5 can select Bulk-transfer or Interrupt-transfer
- EndPoint 1 to 5 is comprised of Double Buffers.
- The size of each endpoint is according to the follows.
- Endpoint 0, 2 to 5: 64 bytes
- Endpoint 1: 256 bytes
- [USB host]
- USB2.0 Full/Low-speed supported
- Bulk-transfer, interrupt-transfer and Isochronous-transfer support
- Automatic detection of connected/disconnected USB Device
- Automatic processing of the IN/OUT token handshake packet
- Max 256-byte packet-length supported
- Wake-up function supported
- [USB device]
- Multi-function Serial Interface (Max 8 channels)
- 4 channels with 16steps ×9-bit FIFO (ch.4 to ch.7), 4 channels without FIFO (ch.0 to ch.3)
- Operation mode is selectable from the followings for each channel.
- UART
- CSIO
- I2C
- [UART]
- Full-duplex double buffer
- Selection with or without parity supported
- Built-in dedicated baud rate generator
- External clock available as a serial clock
- Hardware Flow control: Automatically control the transmission by CTS/RTS (only ch.4)
- Various error detection functions available (parity errors, framing errors, and overrun errors)
- [CSIO]
- Full-duplex double buffer
- Built-in dedicated baud rate generator
- Overrun error detection function available
- [I2C]
- Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported
- DMA Controller (8 channels)
- The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously.
- 8 independently configured and operated channels
- Transfer can be started by software or request from the built-in peripherals
- Transfer address area: 32-bit (4 Gbytes)
- Transfer mode: Block transfer/Burst transfer/Demand transfer
- Transfer data type: byte/half-word/word
- Transfer block count: 1 to 16
- Number of transfers: 1 to 65536
- A/D Converter (Max 24 channels)
- [12-bit A/D Converter]
- Successive Approximation type
- Built-in 2 units
- Conversion time: 2.0 μs to 3.6 V
- Priority conversion available (priority at 2 levels)
- Scanning conversion mode
- Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps)
- [12-bit A/D Converter]
- Base Timer (Max 8 channels)
- Operation mode is selectable from the followings for each channel.
- 16-bit PWM timer
- 16-bit PPG timer
- 16-/32-bit reload timer
- 16-/32-bit PWC timer
- Operation mode is selectable from the followings for each channel.
- General-Purpose I/O Port
- This series can use its pins as general-purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.
- Capable of pull-up control per pin
- Capable of reading pin level directly
- Built-in the port relocate function
- Up to 83 fast general-purpose I/O Ports@100 pin Package Some ports are 5V tolerant I/O.
- Dual Timer (32-/16-bit Down Counter)
- The Dual Timer consists of two programmable 32-/16-bit down counters.
- Operation mode is selectable from the followings for each channel.
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| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 16.8168 | $ 16.82 |
| 200+ | $ 6.7113 | $ 1342.26 |
| 500+ | $ 6.487 | $ 3243.50 |
| 1,190+ | $ 6.3749 | $ 7586.13 |
Standard Packaging1190/Full Tray | ||
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Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | Infineon | |
| Packaging | LQFP-64(12x12) | |
| ADC (Bit) | 12bit | |
| Operating Temperature | -40℃~+85℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 1.65V~3.6V | |
| EEPROM | - | |
| Program Storage Size | 160KB | |
| CPU Core | ARM Cortex-M3 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 40MHz | |
| Oscillator Type | Built-in+External | |
| Number of I/O | 51 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | Infineon | |
| Packaging | LQFP-64(12x12) | |
| ADC (Bit) | 12bit | |
| Operating Temperature | -40℃~+85℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 1.65V~3.6V |
| Type | Description | |
|---|---|---|
| EEPROM | - | |
| Program Storage Size | 160KB | |
| CPU Core | ARM Cortex-M3 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 40MHz | |
| Oscillator Type | Built-in+External | |
| Number of I/O | 51 |
Report an ErrorShow similar products (0) >
Introduction
AI Translation
CY9A340NB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, and Communication Interfaces (USB, UART, CSIO, I²C).
Features
AI Translation
- 32-bit ARM Cortex-M3 Core
- Processor version: r2p1
- Up to 40 MHz Frequency Operation
- Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels
- 24-bit System timer (Sys Tick): System timer for OS task management
- On-chip Memories
- [Flash memory]
- Dual Operation Flash memory has the upper bank and the lower bank. So, this series could implement erase, write and read operations for each bank simultaneously.
- Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank)
- Work area: 32 Kbytes (lower bank)
- Read cycle: 0 wait-cycle Security function for code protection
- [SRAM]
- This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.
- SRAM0: Up to 16 Kbytes SRAM1: Up to 16 Kbytes
- [Flash memory]
- External Bus Interface
- Supports SRAM, NOR Flash memory device
- Up to 8 chip selects
- 8-/16-bit Data width
- Up to 25-bit Address bit
- Maximum area size: Up to 256 Mbytes
- Supports Address/Data multiplex
- Supports external RDY function
- USB Interface
- [USB device]
- USB2.0 Full-Speed supported Max 6 EndPoint supported
- EndPoint 0 is control transfer
- EndPoint 1, 2 can select Bulk-transfer, Interrupt-transfer or Isochronous-transfer
- EndPoint 3 to 5 can select Bulk-transfer or Interrupt-transfer
- EndPoint 1 to 5 is comprised of Double Buffers.
- The size of each endpoint is according to the follows.
- Endpoint 0, 2 to 5: 64 bytes
- Endpoint 1: 256 bytes
- [USB host]
- USB2.0 Full/Low-speed supported
- Bulk-transfer, interrupt-transfer and Isochronous-transfer support
- Automatic detection of connected/disconnected USB Device
- Automatic processing of the IN/OUT token handshake packet
- Max 256-byte packet-length supported
- Wake-up function supported
- [USB device]
- Multi-function Serial Interface (Max 8 channels)
- 4 channels with 16steps ×9-bit FIFO (ch.4 to ch.7), 4 channels without FIFO (ch.0 to ch.3)
- Operation mode is selectable from the followings for each channel.
- UART
- CSIO
- I2C
- [UART]
- Full-duplex double buffer
- Selection with or without parity supported
- Built-in dedicated baud rate generator
- External clock available as a serial clock
- Hardware Flow control: Automatically control the transmission by CTS/RTS (only ch.4)
- Various error detection functions available (parity errors, framing errors, and overrun errors)
- [CSIO]
- Full-duplex double buffer
- Built-in dedicated baud rate generator
- Overrun error detection function available
- [I2C]
- Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported
- DMA Controller (8 channels)
- The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously.
- 8 independently configured and operated channels
- Transfer can be started by software or request from the built-in peripherals
- Transfer address area: 32-bit (4 Gbytes)
- Transfer mode: Block transfer/Burst transfer/Demand transfer
- Transfer data type: byte/half-word/word
- Transfer block count: 1 to 16
- Number of transfers: 1 to 65536
- A/D Converter (Max 24 channels)
- [12-bit A/D Converter]
- Successive Approximation type
- Built-in 2 units
- Conversion time: 2.0 μs to 3.6 V
- Priority conversion available (priority at 2 levels)
- Scanning conversion mode
- Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps)
- [12-bit A/D Converter]
- Base Timer (Max 8 channels)
- Operation mode is selectable from the followings for each channel.
- 16-bit PWM timer
- 16-bit PPG timer
- 16-/32-bit reload timer
- 16-/32-bit PWC timer
- Operation mode is selectable from the followings for each channel.
- General-Purpose I/O Port
- This series can use its pins as general-purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.
- Capable of pull-up control per pin
- Capable of reading pin level directly
- Built-in the port relocate function
- Up to 83 fast general-purpose I/O Ports@100 pin Package Some ports are 5V tolerant I/O.
- Dual Timer (32-/16-bit Down Counter)
- The Dual Timer consists of two programmable 32-/16-bit down counters.
- Operation mode is selectable from the followings for each channel.
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |
Alternative Parts
| MPN | Manufacturer | Packaging | Availability | Unit Price | ||
|---|---|---|---|---|---|---|
| CY9AF142LAPMC-G-JNE2 | Infineon | LQFP-64(12x12) | 0 | $ 14.5095 | ||
| CY9AF342LAPMC-G-JNE2-1 | Infineon | LQFP-64(12x12) | 0 | $ 7.374 | ||
| CY9AFB42LAPMC-G-JNE2 | Infineon | LQFP-64(12x12) | 0 | $ 14.5095 | ||
| CY9AF114LAPMC-GNE2 | Infineon/CYPRESS | LQFP-64(12x12) | 0 | $ 2.2452 | ||
| CY9AF314LAPMC-GNE2 | Infineon/CYPRESS | LQFP-64(12x12) | 0 | $ 5.1422 | ||
| CY9AF144LAPMC-G-JNE2 | Infineon | LQFP-64(12x12) | 0 | $ 14.5095 | ||
| CY9AF344LAPMC-G-JNE2 | Infineon | LQFP-64(12x12) | 0 | $ 16.9031 | ||
| CY9AFB44LAPMC-G-JNE2 | Infineon | LQFP-64(12x12) | 0 | $ 16.9031 | ||
| CY9AFB44LAQN-G-AVE2 | Infineon | LQFP-64(12x12) | 0 | $ 17.0107 | ||
| CY9AFB44LPMC-G-JNE2 | Infineon | LQFP-64(12x12) | 0 | $ 16.9031 |

