micron MT53E1G32D2FW-046 AUT:A
| Manufacturer | |
| MPN | MT53E1G32D2FW-046 AUT:A |
| LCSC Part # | C2889134 |
| Packaging | VFBGA-200 |
| Customer # | |
| Key Attributes | 32Gbit 1.06V~1.17V 2.133GHz LPDDR4X SDRAM VFBGA-200 Memory RoHS |
| Datasheet |
Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | micron | |
| Packaging | VFBGA-200 | |
| Operating Temperature | -40℃~+125℃ | |
| Features | Auto self-refresh;Built-in temperature sensor;Auto precharge function;Write leveling function;ZQ calibration function | |
| Refresh Current | - | |
| Memory Size | 32Gbit | |
| Voltage - Supply | 1.06V~1.17V | |
| Clock Frequency | 2.133GHz | |
| Memory Format | LPDDR4X SDRAM | |
| Current - Supply | - |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | micron | |
| Packaging | VFBGA-200 | |
| Operating Temperature | -40℃~+125℃ | |
| Features | Auto self-refresh;Built-in temperature sensor;Auto precharge function;Write leveling function;ZQ calibration function | |
| Refresh Current | - |
| Type | Description | |
|---|---|---|
| Memory Size | 32Gbit | |
| Voltage - Supply | 1.06V~1.17V | |
| Clock Frequency | 2.133GHz | |
| Memory Format | LPDDR4X SDRAM | |
| Current - Supply | - |
Report an ErrorShow similar products (0) >
Features
AI Translation
- Ultra-low-voltage core and I/O power supplies – VDD1 = 1.70 - 1.95 V; 1.80 V nominal – VDD2 = 1.06 – 1.17 V; 1.10 V nominal – VDDQ = 1.06 – 1.17 V; 1.10 V nominal or low VDDQ = 0.57 - 0.65 V; 0.60 V nominal
- Frequency range – 2133 – 10 MHz (data rate range: 4266 – 20 Mb/s per pin)
- 16n prefetch DDR architecture
- 8 internal banks per channel for concurrent operation
- Single-data-rate CMD/ADR entry
- Bidirectional/differential data strobe per byte lane
- Programmable READ and WRITE latencies (RL/WL)
- Programmable and on-the-fly burst lengths (BL = 16, 32)
- Directed per-bank refresh for concurrent bank operation and ease of command scheduling
- Up to 8.5 GB/s per die
- On-chip temperature sensor to control self refresh rate
- Partial-array self refresh (PASR)
- Selectable output drive strength (DS)
- Clock-stop capability
- RoHS-compliant, “green” packaging
- Programmable VSS (ODT) termination
- Single-ended CK and DQS support
- Improved tRFCab/tRFCpb = 280 ns/140 ns
- AEC-Q100
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| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 85.0039 | $ 85.00 |
| 200+ | $ 32.8962 | $ 6579.24 |
| 500+ | $ 31.7405 | $ 15870.25 |
| 1,000+ | $ 31.1696 | $ 31169.60 |
Standard Packaging2000/Full Reel | ||
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Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | micron | |
| Packaging | VFBGA-200 | |
| Operating Temperature | -40℃~+125℃ | |
| Features | Auto self-refresh;Built-in temperature sensor;Auto precharge function;Write leveling function;ZQ calibration function | |
| Refresh Current | - | |
| Memory Size | 32Gbit | |
| Voltage - Supply | 1.06V~1.17V | |
| Clock Frequency | 2.133GHz | |
| Memory Format | LPDDR4X SDRAM | |
| Current - Supply | - |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | micron | |
| Packaging | VFBGA-200 | |
| Operating Temperature | -40℃~+125℃ | |
| Features | Auto self-refresh;Built-in temperature sensor;Auto precharge function;Write leveling function;ZQ calibration function | |
| Refresh Current | - |
| Type | Description | |
|---|---|---|
| Memory Size | 32Gbit | |
| Voltage - Supply | 1.06V~1.17V | |
| Clock Frequency | 2.133GHz | |
| Memory Format | LPDDR4X SDRAM | |
| Current - Supply | - |
Report an ErrorShow similar products (0) >
Features
AI Translation
- Ultra-low-voltage core and I/O power supplies – VDD1 = 1.70 - 1.95 V; 1.80 V nominal – VDD2 = 1.06 – 1.17 V; 1.10 V nominal – VDDQ = 1.06 – 1.17 V; 1.10 V nominal or low VDDQ = 0.57 - 0.65 V; 0.60 V nominal
- Frequency range – 2133 – 10 MHz (data rate range: 4266 – 20 Mb/s per pin)
- 16n prefetch DDR architecture
- 8 internal banks per channel for concurrent operation
- Single-data-rate CMD/ADR entry
- Bidirectional/differential data strobe per byte lane
- Programmable READ and WRITE latencies (RL/WL)
- Programmable and on-the-fly burst lengths (BL = 16, 32)
- Directed per-bank refresh for concurrent bank operation and ease of command scheduling
- Up to 8.5 GB/s per die
- On-chip temperature sensor to control self refresh rate
- Partial-array self refresh (PASR)
- Selectable output drive strength (DS)
- Clock-stop capability
- RoHS-compliant, “green” packaging
- Programmable VSS (ODT) termination
- Single-ended CK and DQS support
- Improved tRFCab/tRFCpb = 280 ns/140 ns
- AEC-Q100
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Type | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |

