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TI CDCUN1208LPRHBR

Manufacturer
MPN
CDCUN1208LPRHBR
LCSC Part #
C701746
Packaging
VQFN-32-EP(5x5)
Customer #
Key Attributes
Low-power 2:8 fan-out buffer with general-purpose inputs and outputs
Datasheetpdf iconTI CDCUN1208LPRHBR
RoHS Compliance2 documents available
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QtyUnit Price(Reference Only)Total Amount
1+$ 16.0963$ 16.10
10+$ 15.3395$ 153.40
30+$ 14.0294$ 420.88
100+$ 12.8868$ 1288.68
Standard Packaging3000/Full Reel
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Clock/Timing/Clock Buffers, Drivers
ManufacturerTI
PackagingVQFN-32-EP(5x5)
Operating Temperature-40℃~+85℃
Voltage - Supply1.7V~3.63V
FeaturesMulti-channel fan-out/isolation drive;Programmable frequency division and inversion control;Output enable/shutdown
Number of Inputs2
Output Frequency(Max)400MHz
Number of outputs8

Introduction

AI Translation

The CDCUN1208LP is a 2:8 fan-out buffer with a wide operating power supply voltage range, two general-purpose differential/single-ended inputs, and general-purpose outputs (HCSL, LVDS, or LVCMOS) with edge rate control. The clock buffer supports PCIe Gen 1/2/3. One of the device inputs includes a divider that can provide division values of /1, /2, /4, or /8. The CDCUN1208LP is packaged in a 32-pin QFN package, which reduces the size of the solution. This device is very flexible and easy to use. The states of certain specific pins determine the device's configuration when powered on. Alternatively, the CDCUN1208P provides an SPI/I²C port on which a host processor controls the device's settings. The CDCUN1208P offers excellent additional jitter performance and very low power consumption. The output section includes four dedicated power pins that can enable output ports from different power domains. This feature allows the clock device to switch between different LVCOMS levels without the need for an external logic level conversion circuit.

Features

AI Translation
  • Supports PCIe Gen 1/2/3 configuration options (via pin strapping or SPI/I²C)
  • Input types (HCSL, LVDS, LVCMOS)
  • Output types (HCSL, LVDS, LVCMOS)
  • Signal slew rate (slow, medium, fast)
  • Clock input divider (/1, /2, /4, /8) — IN2 only
  • Low-power and power management features, including 1.8V operation and output enable control
  • Integrated voltage regulator for improved PSRR
  • Excellent additive jitter performance
  • LVDS: 200 fs RMS at 100MHz (10kHz to 20MHz)
  • HCSL: 160 fs RMS at 100MHz (10kHz to 20MHz)

Applications

AI Translation
  • Communications and computing systems
  • Factory automation and control
  • Medical imaging
  • Professional audio, video, and signage
  • Motor drivers