GSI Technology GS8182D37BGD-400I

The GS8182D19/37D complies with the SigmaQuad-II+ SRAM pin standard for separate I/O synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs, part of a low-power, low-voltage HSTL I/O SRAM family designed to operate at the speeds required for cost-effective, high-performance networking systems. Separate I/O SRAMs are attractive in applications requiring alternating read and write operations, and the SigmaQuad-II+ SRAM interface and truth table are optimized for alternating read/write. In applications requiring multiple consecutive reads or writes, separate I/O SRAMs are less favored, as burst read/write transfers halve the RAM bandwidth.

• 2.0 clock latency
• Synchronous read/write SigmaQuad interface
• JEDEC standard pinout and package
• Double data rate interface
• Byte write control sampled at data input
• Burst read/write of 4
• 1.8 V +100/-100 mV core power supply
• 1.5 V or 1.8 V HSTL interface
• Pipelined read operation
• Fully coherent read/write pipeline
• ZQ pin for programmable output drive strength
• Data valid pin (QVLD)
• IEEE 1149.1 JTAG-compatible boundary scan
• 165-ball, 13 mm × 15 mm, 1 mm ball pitch BGA package
• RoHS-compliant 165-ball BGA package available

• High-performance network systems