ADI AD9548BCPZ-REEL7

The AD9548 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9548 generates an output clock synchronized to one of up to four differential or eight single- ended external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The AD9548 continuously generates a clean (low jitter), valid output clock even when all references have failed by means of a digitally controlled loop and holdover circuitry. The AD9548 operates over an industrial temperature range of - 40°C to +85°C.

• Supports Stratum 2 stability in holdover mode
• Supports reference switchover with phase build- out
• Supports hitless reference switchover
• Auto/manual holdover and reference switchover
• 4 pairs of reference input pins with each pair configurable as a single differential input or as 2 independent singleended inputs
• Input reference frequencies from 1 Hz to 750 MHz
• Reference validation and frequency monitoring (1 ppm)
• Programmable input reference switchover priority
• 30- bit programmable input reference divider
• 4 pairs of clock output pins with each pair configurable as a single differential LVDS/LVPECL output or as 2 singleended CMOS outputs
• Output frequencies up to 450 MHz
• 30- bit integer and 10- bit fractional programmable feedback divider
• Programmable digital loop filter covering loop bandwidths from 0.001 Hz to 100 kHz
• Optional low noise LC- VCO system clock multiplier
• Optional crystal resonator for system clock input
• On- chip EEPROM to store multiple power- up profiles
• Software controlled power- down
• 88- lead LFCSP package

• Network synchronization
• Cleanup of reference clock jitter
• GPS 1 pulse per second synchronization
• SONET/SDH clocks up to OC- 192, including FEC
• Stratum 2 holdover, jitter cleanup, and phase transient control
• Stratum 3E and Stratum 3 reference clocks
• Wireless base station controllers
• Cable infrastructure
• Data communications