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ADI AD9251BCPZ-65

Manufacturer
MPN
AD9251BCPZ-65
LCSC Part #
C653379
Packaging
LFCSP-64(9x9)
Customer #
Key Attributes
SPI 1.7V~1.9V LFCSP-64(9x9) Analog to Digital Converters (ADC) RoHS
Datasheetpdf iconADI AD9251BCPZ-65
RoHS Compliance1 documents available
Alternative Parts10
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QtyUnit Price(Reference Only)Total Amount
1+$ 36.1118$ 36.11
5+$ 32.9251$ 164.63
30+$ 31.2361$ 937.08
Standard Packaging260/Full Tray
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC)
ManufacturerADI
PackagingLFCSP-64(9x9)
Operating Temperature-40℃~+85℃
InterfaceSPI
Quiescent Current (Iq)-
Voltage - Supply1.7V~1.9V
Number of Channels2
Integral non - linearity0.6LSB
Voltage ReferenceBuilt-in
Clock/OscillatorExternal
Clock Frequency-
FeaturesMulti-chip synchronization
Resolution(Bits)14;65MHz
S/N Ratio74.5dB
ADC architecturePipeline
Programmable Gain-

Introduction

AI Translation

The AD9251 is a monolithic, dual-channel, 1.8 V supply, 14-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported and output data can be multiplexed onto a single output bus. The AD9251 is available in a 64-lead RoHS Compliant LFCSP and is specified over the industrial temperature range (-40°C to +85°C).

Features

AI Translation
  • 1.8 V analog supply operation
  • 1.8 V to 3.3 V output supply
  • SNR 74.3 dBFS at 9.7 MHz input 71.5 dBFS at 200 MHz input
  • SFDR 93 dBc at 9.7 MHz input 80 dBc at 200 MHz input
  • Low power 33 mW per channel at 20 MSPS 73 mW per channel at 80 MSPS
  • Differential input with 700 MHz bandwidth
  • On-chip voltage reference and sample-and-hold circuit
  • 2 V p-p differential analog input
  • DNL = ±0.45 LSB
  • Serial port control options
  • Offset binary, gray code, or twos complement data format
  • Optional clock duty cycle stabilizer
  • Integer 1-to-8 input clock divider
  • Data output multiplex option
  • Built-in selectable digital test pattern generation
  • Energy-saving power-down modes
  • Data clock out with programmable clock and data alignment

Applications

AI Translation
  • Communications
  • Diversity radio systems
  • Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
  • I/Q demodulation systems
  • Smart antenna systems
  • Battery-powered instruments
  • Hand held scope meters
  • Portable medical imaging
  • Ultrasound
  • Radar/LIDAR

Alternative Parts

MPNManufacturerPackagingAvailabilityUnit Price
AD9251BCPZ-80ADILFCSP-64(9x9)200$ 33.1071
AD9251BCPZRL7-65ADILFCSP-64(9x9)0$ 30.4633
AD9251BCPZRL7-80ADILFCSP-64(9x9)0$ 51.209
AD9258BCPZ-105ADILFCSP-64(9x9)0$ 301.1125
AD9640ABCPZ-105ADILFCSP-64(9x9)0$ 244.9965
AD9640ABCPZRL7-80ADILFCSP-64(9x9)0$ 174.4091
AD9640ABCPZ-80ADILFCSP-64(9x9)0$ 149.3801
AD9640ABCPZ-125ADILFCSP-64(9x9)0$ 292.7855
AD9640ABCPZRL7-125ADILFCSP-64(9x9)0$ 292.7855
AD9640ABCPZ-150ADILFCSP-64(9x9)0$ 388.3648