ADI AD6674BCPZ-1000

The AD6674 is a 385 MHz bandwidth mixed-signal IF receiver featuring a dual-channel, 14-bit 1.0 GSPS/750 MSPS/500 MSPS ADC and various DSP blocks, including four wideband DDCs, one NSR, and VDR monitoring. It incorporates an on-chip buffer and sample-and-hold circuit, specifically designed for low power consumption, small size, and ease of use. The product is designed to support communications applications, enabling wideband analog signal sampling up to 2 GHz. The AD6674 is optimized for wide input bandwidth, high sample rate, excellent linearity, low power consumption, and small package size. The dual-channel ADC core employs a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features a wideband input supporting user-selectable input ranges. An integrated voltage reference simplifies design. Both analog input and clock signals are differential. ADC data outputs are internally connected to four DDCs through a crossbar multiplexer. Each DDC contains up to five cascaded signal processing stages: one 12-bit frequency converter (NCO) and up to four half-band decimation filters. The output of each ADC is internally connected to the NSR block. The integrated NSR circuit improves SNR performance over a narrower frequency band within the Nyquist bandwidth. The device supports two different output modes, selectable via SPI. When the NSR feature is enabled, the AD6674 can achieve higher SNR performance within a limited portion of the Nyquist bandwidth while processing ADC output, maintaining 9-bit output resolution. NSR is enabled by default on the AD6674. The output of each ADC is also internally connected to the VDR block. For specified input signals, this optional mode supports full dynamic range. Inputs within the specified exclusion band (based on DPD applications) pass through unchanged. Inputs that violate the specified exclusion band result in reduced output resolution. When using VDR, the dynamic range of the observation receiver is determined by the specified input frequency exclusion band. For signals within the exclusion band, the output is presented at the maximum allowable resolution. For signals exceeding the specified power level within this frequency exclusion band, the output resolution is truncated. This exclusion band is based on DPD applications and supports tunable real IF sampling, zero-IF, or complex IF receiver architectures. The AD6674 DDC, NSR, and VDR operating modes are selectable via SPI-programmable profiles. In addition to the DDC block, the AD6674 includes other features that simplify AGC functionality in communications receivers. Using the fast detect control bits in ADC register 0x245, a programmable threshold detector can monitor input signal power. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Due to the extremely short latency of this threshold indicator, users can quickly reduce system gain to prevent overrange conditions at the ADC input. In addition to the fast detect output, the AD6674 also provides signal monitoring capability. The signal monitor block provides additional information about the signal being digitized by the ADC. Users can configure the JESD204B subclass 1 high-speed serial output in various dual-channel and quad-channel configurations, depending on the DDC configuration and acceptable lane rate of the receive logic device. The SYSREF± and SYNCINB± input pins support multi-device synchronization. The AD6674 offers flexible power-down options that can significantly reduce power consumption when needed. All these features are programmable through a 1.8 V three-wire SPI. The AD6674 is available in a 64-lead lead-free LFCSP package, rated for the −40°C to +85°C industrial temperature range. This product is protected by U.S. patents.

• JESD204B (Subclass 1) encoded serial digital output
• In-band SFDR = 83 dBFS (at 340 MHz, 750 MSPS)
• In-band SNR = 66.7 dBFS (at 340 MHz, 750 MSPS)
• Total power consumption per channel at 750 MSPS: 1.4 W (default settings)
• Noise density = −153 dBFS/Hz (750 MSPS)
• DC supply: 1.25 V, 2.5 V, and 3.3 V
• 95 dB channel isolation/crosstalk
• Amplitude detect bits for efficient AGC implementation
• Noise shaping requantizer (NSR) option for primary receiver functionality
• Variable dynamic range (VDR) option for digital predistortion (DPD) functionality
• 2 integrated wideband digital processors per channel
• 12-bit NCO with up to 4 cascaded half-band filters
• Differential clock input
• Integer clock division: 1, 2, 4, or 8
• Low-power powerdown mode
• Flexible JESD204B lane configuration
• Small signal dither
• Wide full-power bandwidth supporting IF signal sampling up to 2 GHz
• Buffered input with programmable input impedance simplifies filter design and implementation
• Four integrated wideband decimation filters and NCO blocks for multiband receiver support
• Flexible SPI control for product features and functions to meet specific system requirements
• Programmable fast overrange detection and signal monitoring
• 9 mm × 9 mm, 64-lead LFCSP

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