The 74AXP1G57 is a configurable multifunction gate with Schmitt-trigger inputs. The device can be configured for any of the following logic functions: AND, OR, NAND, NOR, XNOR, inverter, and buffer. All inputs can be directly connected to Vcc or GND. The device ensures very low static and dynamic power consumption across the entire Vcc range of 0.7 V to 2.75 V. It fully supports partial power-down applications using IOFF. The IOFF circuit disables the output, preventing potentially damaging backflow current through the device during power-down.

• Configurable multifunction gate with Schmitt-trigger inputs.
• Configurable for the following logic functions: AND, OR, NAND, NOR, XNOR, inverter, and buffer.
• All inputs can be connected directly to Vcc or GND.
• Guaranteed very low static and dynamic power consumption across the entire Vcc range (0.7 V to 2.75 V).
• Fully suitable for partial power-down applications using IOFF. The IOFF circuit disables the output, preventing potentially damaging backflow current through the device when it is powered down.

• Wide supply voltage range: 0.7 V to 2.75 V
• Low input capacitance; C1 = 0.5 pF (typical)
• Low output capacitance; C0 = 1.0 pF (typical)
• Low dynamic power consumption; CPD = 2.7 pF at Vcc = 1.2 V (typical)
• Low static power consumption; ICC = 0.6 μA (85 °C maximum)
• High noise immunity
• JEDEC compliant: JESD8-12A.01 (1.1 V to 1.3 V), JESD8-11A.01 (1.4 V to 1.6 V), JESD8-7A (1.65 V to 1.95 V), JESD8-5A.01 (2.3 V to 2.7 V)
• ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV; CDM JESD22-C101E exceeds 1000 V
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Inputs accept voltages up to 2.75 V
• Low noise overshoot and undershoot <10% of VCC
• IOFF circuit provides partial power-down mode operation
• Multiple package options
• Specified temperature range -40 °C to +85 °C