SILICON LABS 510PAA100M000BAGR

• 3.3, 2.5, or 1.8 V operation
• Differential (LVPECL, LVDS, HCSL) or CMOS output options
• Optional integrated 1:2 CMOS fanout buffer
• Runt suppression on OE and power on
• Industry standard 5×7, 3.2×5, and 2.5×3.2 mm packages
• Pb-free, RoHS compliant
• -40 to 85 ℃ operation
• 3G-SDI/HD-SDI/SDI
• Telecom
• Switches/routers
• FPGA/ASIC clock generation

Utilizes advanced DSPLL technology to provide any frequency from 100 kHz to 250 MHz. Uses one fixed crystal and proprietary DSPLL synthesizer to generate any frequency across this range. Allows the crystal resonator to provide enhanced reliability, improved mechanical robustness, and excellent stability. Provides superior supply noise rejection, simplifying low jitter clock generation in noisy environments. Crystal ESR and DLD are individually production-tested to guarantee performance and enhance reliability. Factory-configurable for a wide variety of user specifications, eliminating long lead times and non-recurring engineering charges associated with custom frequency oscillators.

• Supports any frequency from 100 kHz to 250 MHz
• Low jitter operation
• 2 to 4 week lead times
• Total stability includes 10-year aging
• Comprehensive production test coverage includes crystal ESR and DLD
• On-chip LDO regulator for power supply noise filtering

• SONET/SDH/OTN
• Gigabit Ethernet
• Fibre Channel/SAS/SATA
• PCI Express